i386.md (any_extend): New code iterator.
* config/i386/i386.md (any_extend): New code iterator.
(u, s): New code attributes.
(sgnprefix): Ditto.
(DWIH): Rewrite as code iterator for SI and DI modes.
(DWI): Rewrite as mode attribute.
(dwi): New mode attribute.
(di): Depend on SI mode and DI mode.
(doubleint_general_operand): Remove mode attribute.
(*lea_1): Macroize insn from *lea_1_rex64 and *lea_1 patterns using
DWIH mode iterator.
(*add<mode>3_doubleword): Use DWIH as the base mode iterator.
(*sub<mode>3_doubleword): Ditto.
(mul<mode>3): Macroize expander from mul{hi,si,di}3 patterns
using SWIM248 mode iterator.
(*mul<mode>3_1): Macroize insn from mul{si,di}3_1 patterns
using SWI48 mode iterator.
(<u>mul<mode><dwi>3): Macroize expander from {,u}mul{sidi,diti}3
patterns using DWIH mode iterator and any_extend code iterator.
(<u>mulqihi3): Macroize expander from {,u}mulqihi3 patterns
using any_extend code iterator.
(*<u>mul<mode><dwi>3_1): Macroize insn from {,u}mul{sidi,diti}3_1
patterns using DWIH mode iterator and any_extend code iterator.
(*<u>mulqihi3_1): Macroize insn from {,u}mulqihi3_1 patterns
using any_extend code iterator.
(<s>mul<mode>3_highpart): Macroize expander from
{s,u}mul{si,di}3_highpart patterns using DWIH mode iterator
and any_extend code iterator.
(*<s>muldi3_highpart_1): Macroize insn from
*{s,u}muldi3_highpart_rex64 patterns using any_extend code iterator.
(*<s>mulsi3_highpart_1): Macroize insn from *{s,u}mulsi3_highpart_1
patterns using any_extend code iterator.
(*<s>mulsi3_highpart_zext): Macroize insn from
*{s,u}mulsi3_highpart_zext patterns using any_extend code iterator.
From-SVN: r152539
This commit is contained in:
Uros Bizjak
parent
f484a91ab4
commit
68bc087496
2 changed files with 201 additions and 420 deletions
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@ -1,3 +1,42 @@
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2009-10-07 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (any_extend): New code iterator.
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(u, s): New code attributes.
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(sgnprefix): Ditto.
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(DWIH): Rewrite as code iterator for SI and DI modes.
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(DWI): Rewrite as mode attribute.
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(dwi): New mode attribute.
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(di): Depend on SI mode and DI mode.
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(doubleint_general_operand): Remove mode attribute.
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(*lea_1): Macroize insn from *lea_1_rex64 and *lea_1 patterns using
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DWIH mode iterator.
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(*add<mode>3_doubleword): Use DWIH as the base mode iterator.
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(*sub<mode>3_doubleword): Ditto.
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(mul<mode>3): Macroize expander from mul{hi,si,di}3 patterns
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using SWIM248 mode iterator.
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(*mul<mode>3_1): Macroize insn from mul{si,di}3_1 patterns
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using SWI48 mode iterator.
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(<u>mul<mode><dwi>3): Macroize expander from {,u}mul{sidi,diti}3
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patterns using DWIH mode iterator and any_extend code iterator.
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(<u>mulqihi3): Macroize expander from {,u}mulqihi3 patterns
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using any_extend code iterator.
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(*<u>mul<mode><dwi>3_1): Macroize insn from {,u}mul{sidi,diti}3_1
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patterns using DWIH mode iterator and any_extend code iterator.
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(*<u>mulqihi3_1): Macroize insn from {,u}mulqihi3_1 patterns
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using any_extend code iterator.
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(<s>mul<mode>3_highpart): Macroize expander from
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{s,u}mul{si,di}3_highpart patterns using DWIH mode iterator
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and any_extend code iterator.
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(*<s>muldi3_highpart_1): Macroize insn from
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*{s,u}muldi3_highpart_rex64 patterns using any_extend code iterator.
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(*<s>mulsi3_highpart_1): Macroize insn from *{s,u}mulsi3_highpart_1
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patterns using any_extend code iterator.
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(*<s>mulsi3_highpart_zext): Macroize insn from
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*{s,u}mulsi3_highpart_zext patterns using any_extend code iterator.
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2009-10-07 Jakub Jelinek <jakub@redhat.com>
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* dwarf2out.c (tree_add_const_value_attribute_for_decl): Don't add
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@ -124,10 +163,8 @@
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(enum processor_type): Add PROCESSOR_PPCA2.
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* config/rs6000/rs6000.c (ppca2_cost): New costs.
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(rs6000_override_options): Add "a2" to processor_target_table.
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Update rs6000_always_hint logic. Correctly set rs6000_cost for
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a2.
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* doc/invoke.texi (RS/6000 and PowerPC Options): Document
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-mcpu=a2.
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Update rs6000_always_hint logic. Correctly set rs6000_cost for a2.
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* doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=a2.
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2009-10-06 Uros Bizjak <ubizjak@gmail.com>
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@ -702,6 +702,16 @@
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;; Base name for x87 insn mnemonic.
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(define_code_attr absnegprefix [(abs "abs") (neg "chs")])
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;; Used in signed and unsigned widening multiplications.
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(define_code_iterator any_extend [sign_extend zero_extend])
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;; Various insn prefixes for widening operations.
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(define_code_attr u [(sign_extend "") (zero_extend "u")])
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(define_code_attr s [(sign_extend "s") (zero_extend "u")])
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;; Instruction prefix for widening operations.
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(define_code_attr sgnprefix [(sign_extend "i") (zero_extend "")])
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;; All single word integer modes.
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(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
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@ -720,12 +730,13 @@
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(define_mode_iterator SWIM248 [(HI "TARGET_HIMODE_MATH")
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SI (DI "TARGET_64BIT")])
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;; Double word integer modes.
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(define_mode_iterator DWI [(DI "!TARGET_64BIT")
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(TI "TARGET_64BIT")])
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;; Half mode for double word integer modes.
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(define_mode_attr DWIH [(DI "SI") (TI "DI")])
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(define_mode_iterator DWIH [(SI "!TARGET_64BIT")
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(DI "TARGET_64BIT")])
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;; Double word integer modes.
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(define_mode_attr DWI [(SI "DI") (DI "TI")])
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(define_mode_attr dwi [(SI "di") (DI "ti")])
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;; Instruction suffix for integer modes.
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(define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
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@ -740,7 +751,7 @@
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(define_mode_attr g [(SI "g") (DI "rme")])
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;; Immediate operand constraint for double integer modes.
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(define_mode_attr di [(DI "iF") (TI "e")])
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(define_mode_attr di [(SI "iF") (DI "e")])
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;; General operand predicate for integer modes.
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(define_mode_attr general_operand
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@ -750,11 +761,6 @@
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(DI "x86_64_general_operand")
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(TI "x86_64_general_operand")])
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;; General operand predicate for double integer modes.
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(define_mode_attr doubleint_general_operand
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[(DI "general_operand")
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(TI "x86_64_general_operand")])
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;; SSE and x87 SFmode and DFmode floating point modes
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(define_mode_iterator MODEF [SF DF])
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@ -783,7 +789,6 @@
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;; This mode iterator allows :P to be used for patterns that operate on
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;; pointer-sized quantities. Exactly one of the two alternatives will match.
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(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
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;; Scheduling descriptions
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@ -6090,28 +6095,28 @@
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""
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"ix86_expand_binary_operator (PLUS, <MODE>mode, operands); DONE;")
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(define_insn_and_split "*add<mode>3_doubleword"
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[(set (match_operand:DWI 0 "nonimmediate_operand" "=r,o")
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(plus:DWI
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(match_operand:DWI 1 "nonimmediate_operand" "%0,0")
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(match_operand:DWI 2 "<doubleint_general_operand>" "ro<di>,r<di>")))
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(define_insn_and_split "*add<dwi>3_doubleword"
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[(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o")
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(plus:<DWI>
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(match_operand:<DWI> 1 "nonimmediate_operand" "%0,0")
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(match_operand:<DWI> 2 "<general_operand>" "ro<di>,r<di>")))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
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"ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
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"#"
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"reload_completed"
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[(parallel [(set (reg:CC FLAGS_REG)
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(unspec:CC [(match_dup 1) (match_dup 2)]
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UNSPEC_ADD_CARRY))
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(set (match_dup 0)
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(plus:<DWIH> (match_dup 1) (match_dup 2)))])
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(plus:DWIH (match_dup 1) (match_dup 2)))])
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(parallel [(set (match_dup 3)
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(plus:<DWIH>
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(plus:<DWIH>
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(ltu:<DWIH> (reg:CC FLAGS_REG) (const_int 0))
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(plus:DWIH
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(plus:DWIH
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(ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
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(match_dup 4))
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(match_dup 5)))
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(clobber (reg:CC FLAGS_REG))])]
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"split_<mode> (&operands[0], 3, &operands[0], &operands[3]);")
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"split_<dwi> (&operands[0], 3, &operands[0], &operands[3]);")
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(define_insn "add<mode>3_carry"
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[(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
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@ -6181,32 +6186,15 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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(define_insn "*lea_1_rex64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(match_operand:DI 1 "no_seg_address_operand" "p"))]
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"TARGET_64BIT"
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"lea{q}\t{%a1, %0|%0, %a1}"
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[(set_attr "type" "lea")
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(set_attr "mode" "DI")])
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(define_insn "*lea_1"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(match_operand:SI 1 "no_seg_address_operand" "p"))]
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"!TARGET_64BIT"
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"lea{l}\t{%a1, %0|%0, %a1}"
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[(set (match_operand:DWIH 0 "register_operand" "=r")
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(match_operand:DWIH 1 "no_seg_address_operand" "p"))]
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""
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"lea{<imodesuffix>}\t{%a1, %0|%0, %a1}"
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[(set_attr "type" "lea")
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(set_attr "mode" "SI")])
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(set_attr "mode" "<MODE>")])
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(define_insn "*lea_1_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
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"TARGET_64BIT"
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"lea{l}\t{%a1, %k0|%k0, %a1}"
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[(set_attr "type" "lea")
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(set_attr "mode" "SI")])
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(define_insn "*lea_2_rex64"
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(define_insn "*lea_2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
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"TARGET_64BIT"
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@ -6214,6 +6202,15 @@
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[(set_attr "type" "lea")
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(set_attr "mode" "SI")])
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(define_insn "*lea_2_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
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"TARGET_64BIT"
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"lea{l}\t{%a1, %k0|%k0, %a1}"
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[(set_attr "type" "lea")
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(set_attr "mode" "SI")])
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(define_insn "*add<mode>_1"
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[(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r")
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(plus:SWI48
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@ -7624,11 +7621,11 @@
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""
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"ix86_expand_binary_operator (MINUS, <MODE>mode, operands); DONE;")
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(define_insn_and_split "*sub<mode>3_doubleword"
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[(set (match_operand:DWI 0 "nonimmediate_operand" "=r,o")
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(minus:DWI
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(match_operand:DWI 1 "nonimmediate_operand" "0,0")
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(match_operand:DWI 2 "<doubleint_general_operand>" "ro<di>,r<di>")))
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(define_insn_and_split "*sub<dwi>3_doubleword"
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[(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o")
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(minus:<DWI>
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(match_operand:<DWI> 1 "nonimmediate_operand" "0,0")
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(match_operand:<DWI> 2 "<general_operand>" "ro<di>,r<di>")))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
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"#"
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@ -7636,15 +7633,15 @@
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[(parallel [(set (reg:CC FLAGS_REG)
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(compare:CC (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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(minus:<DWIH> (match_dup 1) (match_dup 2)))])
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(minus:DWIH (match_dup 1) (match_dup 2)))])
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(parallel [(set (match_dup 3)
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(minus:<DWIH>
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(minus:DWIH
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(match_dup 4)
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(plus:<DWIH>
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(ltu:<DWIH> (reg:CC FLAGS_REG) (const_int 0))
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(plus:DWIH
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(ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
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(match_dup 5))))
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(clobber (reg:CC FLAGS_REG))])]
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"split_<mode> (&operands[0], 3, &operands[0], &operands[3]);")
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"split_<dwi> (&operands[0], 3, &operands[0], &operands[3]);")
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(define_insn "sub<mode>3_carry"
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[(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
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@ -7826,77 +7823,43 @@
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;; Multiply instructions
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(define_expand "muldi3"
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[(parallel [(set (match_operand:DI 0 "register_operand" "")
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(mult:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "x86_64_general_operand" "")))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_64BIT"
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"")
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;; On AMDFAM10
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;; IMUL reg64, reg64, imm8 Direct
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;; IMUL reg64, mem64, imm8 VectorPath
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;; IMUL reg64, reg64, imm32 Direct
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;; IMUL reg64, mem64, imm32 VectorPath
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;; IMUL reg64, reg64 Direct
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;; IMUL reg64, mem64 Direct
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(define_insn "*muldi3_1_rex64"
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[(set (match_operand:DI 0 "register_operand" "=r,r,r")
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(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
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(match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT
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&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
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"@
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imul{q}\t{%2, %1, %0|%0, %1, %2}
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imul{q}\t{%2, %1, %0|%0, %1, %2}
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imul{q}\t{%2, %0|%0, %2}"
|
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[(set_attr "type" "imul")
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(set_attr "prefix_0f" "0,0,1")
|
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(set (attr "athlon_decode")
|
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(cond [(eq_attr "cpu" "athlon")
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(const_string "vector")
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(eq_attr "alternative" "1")
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(const_string "vector")
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(and (eq_attr "alternative" "2")
|
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(match_operand 1 "memory_operand" ""))
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(const_string "vector")]
|
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(const_string "direct")))
|
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(set (attr "amdfam10_decode")
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(cond [(and (eq_attr "alternative" "0,1")
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(match_operand 1 "memory_operand" ""))
|
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(const_string "vector")]
|
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(const_string "direct")))
|
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(set_attr "mode" "DI")])
|
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|
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(define_expand "mulsi3"
|
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(mult:SI (match_operand:SI 1 "register_operand" "")
|
||||
(match_operand:SI 2 "general_operand" "")))
|
||||
(define_expand "mul<mode>3"
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[(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
|
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(mult:SWIM248
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(match_operand:SWIM248 1 "register_operand" "")
|
||||
(match_operand:SWIM248 2 "<general_operand>" "")))
|
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(clobber (reg:CC FLAGS_REG))])]
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""
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"")
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||||
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;; On AMDFAM10
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;; IMUL reg32, reg32, imm8 Direct
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;; IMUL reg32, mem32, imm8 VectorPath
|
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;; IMUL reg32, reg32, imm32 Direct
|
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;; IMUL reg32, mem32, imm32 VectorPath
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;; IMUL reg32, reg32 Direct
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;; IMUL reg32, mem32 Direct
|
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(define_expand "mulqi3"
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[(parallel [(set (match_operand:QI 0 "register_operand" "")
|
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(mult:QI
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(match_operand:QI 1 "register_operand" "")
|
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(match_operand:QI 2 "nonimmediate_operand" "")))
|
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(clobber (reg:CC FLAGS_REG))])]
|
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"TARGET_QIMODE_MATH"
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"")
|
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|
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(define_insn "*mulsi3_1"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
|
||||
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
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(match_operand:SI 2 "general_operand" "K,i,mr")))
|
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;; On AMDFAM10
|
||||
;; IMUL reg32/64, reg32/64, imm8 Direct
|
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;; IMUL reg32/64, mem32/64, imm8 VectorPath
|
||||
;; IMUL reg32/64, reg32/64, imm32 Direct
|
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;; IMUL reg32/64, mem32/64, imm32 VectorPath
|
||||
;; IMUL reg32/64, reg32/64 Direct
|
||||
;; IMUL reg32/64, mem32/64 Direct
|
||||
|
||||
(define_insn "*mul<mode>3_1"
|
||||
[(set (match_operand:SWI48 0 "register_operand" "=r,r,r")
|
||||
(mult:SWI48
|
||||
(match_operand:SWI48 1 "nonimmediate_operand" "%rm,rm,0")
|
||||
(match_operand:SWI48 2 "<general_operand>" "K,<i>,mr")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"@
|
||||
imul{l}\t{%2, %1, %0|%0, %1, %2}
|
||||
imul{l}\t{%2, %1, %0|%0, %1, %2}
|
||||
imul{l}\t{%2, %0|%0, %2}"
|
||||
imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
|
||||
imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
|
||||
imul{<imodesuffix>}\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "prefix_0f" "0,0,1")
|
||||
(set (attr "athlon_decode")
|
||||
|
|
@ -7913,7 +7876,7 @@
|
|||
(match_operand 1 "memory_operand" ""))
|
||||
(const_string "vector")]
|
||||
(const_string "direct")))
|
||||
(set_attr "mode" "SI")])
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*mulsi3_1_zext"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
|
||||
|
|
@ -7945,14 +7908,6 @@
|
|||
(const_string "direct")))
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_expand "mulhi3"
|
||||
[(parallel [(set (match_operand:HI 0 "register_operand" "")
|
||||
(mult:HI (match_operand:HI 1 "register_operand" "")
|
||||
(match_operand:HI 2 "general_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_HIMODE_MATH"
|
||||
"")
|
||||
|
||||
;; On AMDFAM10
|
||||
;; IMUL reg16, reg16, imm8 VectorPath
|
||||
;; IMUL reg16, mem16, imm8 VectorPath
|
||||
|
|
@ -7960,12 +7915,14 @@
|
|||
;; IMUL reg16, mem16, imm16 VectorPath
|
||||
;; IMUL reg16, reg16 Direct
|
||||
;; IMUL reg16, mem16 Direct
|
||||
|
||||
(define_insn "*mulhi3_1"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,r,r")
|
||||
(mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
|
||||
(match_operand:HI 2 "general_operand" "K,n,mr")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"TARGET_HIMODE_MATH
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"@
|
||||
imul{w}\t{%2, %1, %0|%0, %1, %2}
|
||||
imul{w}\t{%2, %1, %0|%0, %1, %2}
|
||||
|
|
@ -7984,14 +7941,6 @@
|
|||
(const_string "direct")))
|
||||
(set_attr "mode" "HI")])
|
||||
|
||||
(define_expand "mulqi3"
|
||||
[(parallel [(set (match_operand:QI 0 "register_operand" "")
|
||||
(mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
|
||||
(match_operand:QI 2 "register_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_QIMODE_MATH"
|
||||
"")
|
||||
|
||||
;;On AMDFAM10
|
||||
;; MUL reg8 Direct
|
||||
;; MUL mem8 Direct
|
||||
|
|
@ -8013,24 +7962,58 @@
|
|||
(set_attr "amdfam10_decode" "direct")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_expand "umulqihi3"
|
||||
(define_expand "<u>mul<mode><dwi>3"
|
||||
[(parallel [(set (match_operand:<DWI> 0 "register_operand" "")
|
||||
(mult:<DWI>
|
||||
(any_extend:<DWI>
|
||||
(match_operand:DWIH 1 "nonimmediate_operand" ""))
|
||||
(any_extend:<DWI>
|
||||
(match_operand:DWIH 2 "register_operand" ""))))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "<u>mulqihi3"
|
||||
[(parallel [(set (match_operand:HI 0 "register_operand" "")
|
||||
(mult:HI (zero_extend:HI
|
||||
(match_operand:QI 1 "nonimmediate_operand" ""))
|
||||
(zero_extend:HI
|
||||
(match_operand:QI 2 "register_operand" ""))))
|
||||
(mult:HI
|
||||
(any_extend:HI
|
||||
(match_operand:QI 1 "nonimmediate_operand" ""))
|
||||
(any_extend:HI
|
||||
(match_operand:QI 2 "register_operand" ""))))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_QIMODE_MATH"
|
||||
"")
|
||||
|
||||
(define_insn "*umulqihi3_1"
|
||||
(define_insn "*<u>mul<mode><dwi>3_1"
|
||||
[(set (match_operand:<DWI> 0 "register_operand" "=A")
|
||||
(mult:<DWI>
|
||||
(any_extend:<DWI>
|
||||
(match_operand:DWIH 1 "nonimmediate_operand" "%0"))
|
||||
(any_extend:<DWI>
|
||||
(match_operand:DWIH 2 "nonimmediate_operand" "rm"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"<sgnprefix>mul{<imodesuffix>}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set (attr "athlon_decode")
|
||||
(if_then_else (eq_attr "cpu" "athlon")
|
||||
(const_string "vector")
|
||||
(const_string "double")))
|
||||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*<u>mulqihi3_1"
|
||||
[(set (match_operand:HI 0 "register_operand" "=a")
|
||||
(mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
|
||||
(zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
|
||||
(mult:HI
|
||||
(any_extend:HI
|
||||
(match_operand:QI 1 "nonimmediate_operand" "%0"))
|
||||
(any_extend:HI
|
||||
(match_operand:QI 2 "nonimmediate_operand" "qm"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_QIMODE_MATH
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"mul{b}\t%2"
|
||||
"<sgnprefix>mul{b}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set (attr "athlon_decode")
|
||||
|
|
@ -8040,168 +8023,36 @@
|
|||
(set_attr "amdfam10_decode" "direct")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_expand "mulqihi3"
|
||||
[(parallel [(set (match_operand:HI 0 "register_operand" "")
|
||||
(mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
|
||||
(sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
|
||||
(define_expand "<s>mul<mode>3_highpart"
|
||||
[(parallel [(set (match_operand:SWI48 0 "register_operand" "")
|
||||
(truncate:SWI48
|
||||
(lshiftrt:<DWI>
|
||||
(mult:<DWI>
|
||||
(any_extend:<DWI>
|
||||
(match_operand:SWI48 1 "nonimmediate_operand" ""))
|
||||
(any_extend:<DWI>
|
||||
(match_operand:SWI48 2 "register_operand" "")))
|
||||
(match_dup 4))))
|
||||
(clobber (match_scratch:SWI48 3 ""))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_QIMODE_MATH"
|
||||
"")
|
||||
""
|
||||
"operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
|
||||
|
||||
(define_insn "*mulqihi3_insn"
|
||||
[(set (match_operand:HI 0 "register_operand" "=a")
|
||||
(mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
|
||||
(sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_QIMODE_MATH
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"imul{b}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set (attr "athlon_decode")
|
||||
(if_then_else (eq_attr "cpu" "athlon")
|
||||
(const_string "vector")
|
||||
(const_string "direct")))
|
||||
(set_attr "amdfam10_decode" "direct")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_expand "umulditi3"
|
||||
[(parallel [(set (match_operand:TI 0 "register_operand" "")
|
||||
(mult:TI (zero_extend:TI
|
||||
(match_operand:DI 1 "nonimmediate_operand" ""))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "register_operand" ""))))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_64BIT"
|
||||
"")
|
||||
|
||||
(define_insn "*umulditi3_insn"
|
||||
[(set (match_operand:TI 0 "register_operand" "=A")
|
||||
(mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
|
||||
(zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_64BIT
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"mul{q}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set (attr "athlon_decode")
|
||||
(if_then_else (eq_attr "cpu" "athlon")
|
||||
(const_string "vector")
|
||||
(const_string "double")))
|
||||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
|
||||
(define_expand "umulsidi3"
|
||||
[(parallel [(set (match_operand:DI 0 "register_operand" "")
|
||||
(mult:DI (zero_extend:DI
|
||||
(match_operand:SI 1 "nonimmediate_operand" ""))
|
||||
(zero_extend:DI
|
||||
(match_operand:SI 2 "register_operand" ""))))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"!TARGET_64BIT"
|
||||
"")
|
||||
|
||||
(define_insn "*umulsidi3_insn"
|
||||
[(set (match_operand:DI 0 "register_operand" "=A")
|
||||
(mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
|
||||
(zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"!TARGET_64BIT
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"mul{l}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set (attr "athlon_decode")
|
||||
(if_then_else (eq_attr "cpu" "athlon")
|
||||
(const_string "vector")
|
||||
(const_string "double")))
|
||||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_expand "mulditi3"
|
||||
[(parallel [(set (match_operand:TI 0 "register_operand" "")
|
||||
(mult:TI (sign_extend:TI
|
||||
(match_operand:DI 1 "nonimmediate_operand" ""))
|
||||
(sign_extend:TI
|
||||
(match_operand:DI 2 "register_operand" ""))))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_64BIT"
|
||||
"")
|
||||
|
||||
(define_insn "*mulditi3_insn"
|
||||
[(set (match_operand:TI 0 "register_operand" "=A")
|
||||
(mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
|
||||
(sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_64BIT
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"imul{q}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set (attr "athlon_decode")
|
||||
(if_then_else (eq_attr "cpu" "athlon")
|
||||
(const_string "vector")
|
||||
(const_string "double")))
|
||||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_expand "mulsidi3"
|
||||
[(parallel [(set (match_operand:DI 0 "register_operand" "")
|
||||
(mult:DI (sign_extend:DI
|
||||
(match_operand:SI 1 "nonimmediate_operand" ""))
|
||||
(sign_extend:DI
|
||||
(match_operand:SI 2 "register_operand" ""))))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"!TARGET_64BIT"
|
||||
"")
|
||||
|
||||
(define_insn "*mulsidi3_insn"
|
||||
[(set (match_operand:DI 0 "register_operand" "=A")
|
||||
(mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
|
||||
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"!TARGET_64BIT
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"imul{l}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set (attr "athlon_decode")
|
||||
(if_then_else (eq_attr "cpu" "athlon")
|
||||
(const_string "vector")
|
||||
(const_string "double")))
|
||||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_expand "umuldi3_highpart"
|
||||
[(parallel [(set (match_operand:DI 0 "register_operand" "")
|
||||
(truncate:DI
|
||||
(lshiftrt:TI
|
||||
(mult:TI (zero_extend:TI
|
||||
(match_operand:DI 1 "nonimmediate_operand" ""))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "register_operand" "")))
|
||||
(const_int 64))))
|
||||
(clobber (match_scratch:DI 3 ""))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_64BIT"
|
||||
"")
|
||||
|
||||
(define_insn "*umuldi3_highpart_rex64"
|
||||
(define_insn "*<s>muldi3_highpart_1"
|
||||
[(set (match_operand:DI 0 "register_operand" "=d")
|
||||
(truncate:DI
|
||||
(lshiftrt:TI
|
||||
(mult:TI (zero_extend:TI
|
||||
(match_operand:DI 1 "nonimmediate_operand" "%a"))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "nonimmediate_operand" "rm")))
|
||||
(mult:TI
|
||||
(any_extend:TI
|
||||
(match_operand:DI 1 "nonimmediate_operand" "%a"))
|
||||
(any_extend:TI
|
||||
(match_operand:DI 2 "nonimmediate_operand" "rm")))
|
||||
(const_int 64))))
|
||||
(clobber (match_scratch:DI 3 "=1"))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_64BIT
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"mul{q}\t%2"
|
||||
"<sgnprefix>mul{q}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set (attr "athlon_decode")
|
||||
|
|
@ -8211,33 +8062,20 @@
|
|||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_expand "umulsi3_highpart"
|
||||
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
||||
(truncate:SI
|
||||
(lshiftrt:DI
|
||||
(mult:DI (zero_extend:DI
|
||||
(match_operand:SI 1 "nonimmediate_operand" ""))
|
||||
(zero_extend:DI
|
||||
(match_operand:SI 2 "register_operand" "")))
|
||||
(const_int 32))))
|
||||
(clobber (match_scratch:SI 3 ""))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_insn "*umulsi3_highpart_insn"
|
||||
(define_insn "*<s>mulsi3_highpart_1"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(truncate:SI
|
||||
(lshiftrt:DI
|
||||
(mult:DI (zero_extend:DI
|
||||
(match_operand:SI 1 "nonimmediate_operand" "%a"))
|
||||
(zero_extend:DI
|
||||
(match_operand:SI 2 "nonimmediate_operand" "rm")))
|
||||
(mult:DI
|
||||
(any_extend:DI
|
||||
(match_operand:SI 1 "nonimmediate_operand" "%a"))
|
||||
(any_extend:DI
|
||||
(match_operand:SI 2 "nonimmediate_operand" "rm")))
|
||||
(const_int 32))))
|
||||
(clobber (match_scratch:SI 3 "=1"))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"mul{l}\t%2"
|
||||
"<sgnprefix>mul{l}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set (attr "athlon_decode")
|
||||
|
|
@ -8247,20 +8085,20 @@
|
|||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "*umulsi3_highpart_zext"
|
||||
(define_insn "*<s>mulsi3_highpart_zext"
|
||||
[(set (match_operand:DI 0 "register_operand" "=d")
|
||||
(zero_extend:DI (truncate:SI
|
||||
(lshiftrt:DI
|
||||
(mult:DI (zero_extend:DI
|
||||
(mult:DI (any_extend:DI
|
||||
(match_operand:SI 1 "nonimmediate_operand" "%a"))
|
||||
(zero_extend:DI
|
||||
(any_extend:DI
|
||||
(match_operand:SI 2 "nonimmediate_operand" "rm")))
|
||||
(const_int 32)))))
|
||||
(clobber (match_scratch:SI 3 "=1"))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_64BIT
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"mul{l}\t%2"
|
||||
"<sgnprefix>mul{l}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set (attr "athlon_decode")
|
||||
|
|
@ -8270,99 +8108,6 @@
|
|||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_expand "smuldi3_highpart"
|
||||
[(parallel [(set (match_operand:DI 0 "register_operand" "")
|
||||
(truncate:DI
|
||||
(lshiftrt:TI
|
||||
(mult:TI (sign_extend:TI
|
||||
(match_operand:DI 1 "nonimmediate_operand" ""))
|
||||
(sign_extend:TI
|
||||
(match_operand:DI 2 "register_operand" "")))
|
||||
(const_int 64))))
|
||||
(clobber (match_scratch:DI 3 ""))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_64BIT"
|
||||
"")
|
||||
|
||||
(define_insn "*smuldi3_highpart_rex64"
|
||||
[(set (match_operand:DI 0 "register_operand" "=d")
|
||||
(truncate:DI
|
||||
(lshiftrt:TI
|
||||
(mult:TI (sign_extend:TI
|
||||
(match_operand:DI 1 "nonimmediate_operand" "%a"))
|
||||
(sign_extend:TI
|
||||
(match_operand:DI 2 "nonimmediate_operand" "rm")))
|
||||
(const_int 64))))
|
||||
(clobber (match_scratch:DI 3 "=1"))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_64BIT
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"imul{q}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set (attr "athlon_decode")
|
||||
(if_then_else (eq_attr "cpu" "athlon")
|
||||
(const_string "vector")
|
||||
(const_string "double")))
|
||||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_expand "smulsi3_highpart"
|
||||
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
||||
(truncate:SI
|
||||
(lshiftrt:DI
|
||||
(mult:DI (sign_extend:DI
|
||||
(match_operand:SI 1 "nonimmediate_operand" ""))
|
||||
(sign_extend:DI
|
||||
(match_operand:SI 2 "register_operand" "")))
|
||||
(const_int 32))))
|
||||
(clobber (match_scratch:SI 3 ""))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_insn "*smulsi3_highpart_insn"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(truncate:SI
|
||||
(lshiftrt:DI
|
||||
(mult:DI (sign_extend:DI
|
||||
(match_operand:SI 1 "nonimmediate_operand" "%a"))
|
||||
(sign_extend:DI
|
||||
(match_operand:SI 2 "nonimmediate_operand" "rm")))
|
||||
(const_int 32))))
|
||||
(clobber (match_scratch:SI 3 "=1"))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"imul{l}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set (attr "athlon_decode")
|
||||
(if_then_else (eq_attr "cpu" "athlon")
|
||||
(const_string "vector")
|
||||
(const_string "double")))
|
||||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "*smulsi3_highpart_zext"
|
||||
[(set (match_operand:DI 0 "register_operand" "=d")
|
||||
(zero_extend:DI (truncate:SI
|
||||
(lshiftrt:DI
|
||||
(mult:DI (sign_extend:DI
|
||||
(match_operand:SI 1 "nonimmediate_operand" "%a"))
|
||||
(sign_extend:DI
|
||||
(match_operand:SI 2 "nonimmediate_operand" "rm")))
|
||||
(const_int 32)))))
|
||||
(clobber (match_scratch:SI 3 "=1"))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_64BIT
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"imul{l}\t%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set (attr "athlon_decode")
|
||||
(if_then_else (eq_attr "cpu" "athlon")
|
||||
(const_string "vector")
|
||||
(const_string "double")))
|
||||
(set_attr "amdfam10_decode" "double")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
;; The patterns that match these are at the end of this file.
|
||||
|
||||
(define_expand "mulxf3"
|
||||
|
|
@ -8379,7 +8124,6 @@
|
|||
"(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
|
||||
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
|
||||
"")
|
||||
|
||||
|
||||
;; Divide instructions
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue