gcc/
2015-01-21 David Sherwood <david.sherwood@arm.com> Tejas Belagod <Tejas.Belagod@arm.com> * config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist) (aarch64_reverse_mask): New decls. * config/aarch64/iterators.md (UNSPEC_REV_REGLIST): New enum. (insn_count): New mode_attr. * config/aarch64/aarch64-simd.md (vec_store_lanesoi, vec_store_lanesci) (vec_store_lanesxi, vec_load_lanesoi, vec_load_lanesci) (vec_load_lanesxi): Made ABI compliant for Big Endian targets. (aarch64_rev_reglist, aarch64_simd_ld2, aarch64_simd_ld3) (aarch64_simd_ld4, aarch64_simd_st2, aarch64_simd_st3) (aarch64_simd_st4): New patterns. * config/aarch64/aarch64.c (aarch64_simd_attr_length_rglist) (aarch64_reverse_mask): New functions. Co-Authored-By: Tejas Belagod <tejas.belagod@arm.com> From-SVN: r219959
This commit is contained in:
David Sherwood
Richard Sandiford
parent
2d8c6dc1d9
commit
668046d175
5 changed files with 195 additions and 6 deletions
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@ -1,3 +1,19 @@
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2015-01-21 David Sherwood <david.sherwood@arm.com>
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Tejas Belagod <Tejas.Belagod@arm.com>
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* config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist)
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(aarch64_reverse_mask): New decls.
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* config/aarch64/iterators.md (UNSPEC_REV_REGLIST): New enum.
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(insn_count): New mode_attr.
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* config/aarch64/aarch64-simd.md (vec_store_lanesoi, vec_store_lanesci)
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(vec_store_lanesxi, vec_load_lanesoi, vec_load_lanesci)
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(vec_load_lanesxi): Made ABI compliant for Big Endian targets.
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(aarch64_rev_reglist, aarch64_simd_ld2, aarch64_simd_ld3)
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(aarch64_simd_ld4, aarch64_simd_st2, aarch64_simd_st3)
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(aarch64_simd_st4): New patterns.
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* config/aarch64/aarch64.c (aarch64_simd_attr_length_rglist)
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(aarch64_reverse_mask): New functions.
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2015-01-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-protos.h (aarch64_simd_disambiguate_copy):
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@ -203,6 +203,8 @@ bool aarch64_modes_tieable_p (machine_mode mode1,
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bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);
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bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context,
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machine_mode);
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int aarch64_simd_attr_length_rglist (enum machine_mode);
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rtx aarch64_reverse_mask (enum machine_mode);
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bool aarch64_offset_7bit_signed_scaled_p (machine_mode, HOST_WIDE_INT);
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char *aarch64_output_scalar_simd_mov_immediate (rtx, machine_mode);
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char *aarch64_output_simd_mov_immediate (rtx, machine_mode, unsigned);
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@ -3880,7 +3880,7 @@
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;; Patterns for vector struct loads and stores.
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(define_insn "vec_load_lanesoi<mode>"
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(define_insn "aarch64_simd_ld2<mode>"
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[(set (match_operand:OI 0 "register_operand" "=w")
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(unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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@ -3912,7 +3912,26 @@
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[(set_attr "type" "neon_load2_one_lane")]
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)
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(define_insn "vec_store_lanesoi<mode>"
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(define_expand "vec_load_lanesoi<mode>"
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[(set (match_operand:OI 0 "register_operand" "=w")
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(unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_LD2))]
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"TARGET_SIMD"
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{
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if (BYTES_BIG_ENDIAN)
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{
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rtx tmp = gen_reg_rtx (OImode);
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rtx mask = aarch64_reverse_mask (<MODE>mode);
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emit_insn (gen_aarch64_simd_ld2<mode> (tmp, operands[1]));
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emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
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}
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else
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emit_insn (gen_aarch64_simd_ld2<mode> (operands[0], operands[1]));
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DONE;
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})
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(define_insn "aarch64_simd_st2<mode>"
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[(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv")
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(unspec:OI [(match_operand:OI 1 "register_operand" "w")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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@ -3933,7 +3952,26 @@
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[(set_attr "type" "neon_store3_one_lane<q>")]
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)
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(define_insn "vec_load_lanesci<mode>"
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(define_expand "vec_store_lanesoi<mode>"
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[(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv")
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(unspec:OI [(match_operand:OI 1 "register_operand" "w")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_ST2))]
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"TARGET_SIMD"
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{
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if (BYTES_BIG_ENDIAN)
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{
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rtx tmp = gen_reg_rtx (OImode);
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rtx mask = aarch64_reverse_mask (<MODE>mode);
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emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
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emit_insn (gen_aarch64_simd_st2<mode> (operands[0], tmp));
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}
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else
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emit_insn (gen_aarch64_simd_st2<mode> (operands[0], operands[1]));
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DONE;
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})
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(define_insn "aarch64_simd_ld3<mode>"
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[(set (match_operand:CI 0 "register_operand" "=w")
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(unspec:CI [(match_operand:CI 1 "aarch64_simd_struct_operand" "Utv")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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@ -3965,7 +4003,26 @@
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[(set_attr "type" "neon_load3_one_lane")]
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)
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(define_insn "vec_store_lanesci<mode>"
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(define_expand "vec_load_lanesci<mode>"
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[(set (match_operand:CI 0 "register_operand" "=w")
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(unspec:CI [(match_operand:CI 1 "aarch64_simd_struct_operand" "Utv")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_LD3))]
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"TARGET_SIMD"
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{
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if (BYTES_BIG_ENDIAN)
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{
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rtx tmp = gen_reg_rtx (CImode);
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rtx mask = aarch64_reverse_mask (<MODE>mode);
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emit_insn (gen_aarch64_simd_ld3<mode> (tmp, operands[1]));
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emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
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}
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else
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emit_insn (gen_aarch64_simd_ld3<mode> (operands[0], operands[1]));
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DONE;
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})
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(define_insn "aarch64_simd_st3<mode>"
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[(set (match_operand:CI 0 "aarch64_simd_struct_operand" "=Utv")
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(unspec:CI [(match_operand:CI 1 "register_operand" "w")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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@ -3986,7 +4043,26 @@
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[(set_attr "type" "neon_store3_one_lane<q>")]
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)
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(define_insn "vec_load_lanesxi<mode>"
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(define_expand "vec_store_lanesci<mode>"
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[(set (match_operand:CI 0 "aarch64_simd_struct_operand" "=Utv")
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(unspec:CI [(match_operand:CI 1 "register_operand" "w")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_ST3))]
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"TARGET_SIMD"
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{
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if (BYTES_BIG_ENDIAN)
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{
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rtx tmp = gen_reg_rtx (CImode);
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rtx mask = aarch64_reverse_mask (<MODE>mode);
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emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
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emit_insn (gen_aarch64_simd_st3<mode> (operands[0], tmp));
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}
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else
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emit_insn (gen_aarch64_simd_st3<mode> (operands[0], operands[1]));
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DONE;
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})
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(define_insn "aarch64_simd_ld4<mode>"
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[(set (match_operand:XI 0 "register_operand" "=w")
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(unspec:XI [(match_operand:XI 1 "aarch64_simd_struct_operand" "Utv")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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@ -4018,7 +4094,26 @@
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[(set_attr "type" "neon_load4_one_lane")]
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)
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(define_insn "vec_store_lanesxi<mode>"
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(define_expand "vec_load_lanesxi<mode>"
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[(set (match_operand:XI 0 "register_operand" "=w")
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(unspec:XI [(match_operand:XI 1 "aarch64_simd_struct_operand" "Utv")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_LD4))]
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"TARGET_SIMD"
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{
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if (BYTES_BIG_ENDIAN)
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{
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rtx tmp = gen_reg_rtx (XImode);
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rtx mask = aarch64_reverse_mask (<MODE>mode);
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emit_insn (gen_aarch64_simd_ld4<mode> (tmp, operands[1]));
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emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
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}
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else
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emit_insn (gen_aarch64_simd_ld4<mode> (operands[0], operands[1]));
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DONE;
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})
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(define_insn "aarch64_simd_st4<mode>"
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[(set (match_operand:XI 0 "aarch64_simd_struct_operand" "=Utv")
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(unspec:XI [(match_operand:XI 1 "register_operand" "w")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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@ -4039,6 +4134,50 @@
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[(set_attr "type" "neon_store4_one_lane<q>")]
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)
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(define_expand "vec_store_lanesxi<mode>"
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[(set (match_operand:XI 0 "aarch64_simd_struct_operand" "=Utv")
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(unspec:XI [(match_operand:XI 1 "register_operand" "w")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_ST4))]
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"TARGET_SIMD"
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{
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if (BYTES_BIG_ENDIAN)
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{
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rtx tmp = gen_reg_rtx (XImode);
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rtx mask = aarch64_reverse_mask (<MODE>mode);
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emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
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emit_insn (gen_aarch64_simd_st4<mode> (operands[0], tmp));
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}
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else
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emit_insn (gen_aarch64_simd_st4<mode> (operands[0], operands[1]));
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DONE;
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})
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(define_insn_and_split "aarch64_rev_reglist<mode>"
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[(set (match_operand:VSTRUCT 0 "register_operand" "=&w")
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(unspec:VSTRUCT
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[(match_operand:VSTRUCT 1 "register_operand" "w")
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(match_operand:V16QI 2 "register_operand" "w")]
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UNSPEC_REV_REGLIST))]
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"TARGET_SIMD"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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int i;
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int nregs = GET_MODE_SIZE (<MODE>mode) / UNITS_PER_VREG;
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for (i = 0; i < nregs; i++)
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{
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rtx op0 = gen_rtx_REG (V16QImode, REGNO (operands[0]) + i);
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rtx op1 = gen_rtx_REG (V16QImode, REGNO (operands[1]) + i);
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emit_insn (gen_aarch64_tbl1v16qi (op0, op1, operands[2]));
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}
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DONE;
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}
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[(set_attr "type" "neon_tbl1_q")
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(set_attr "length" "<insn_count>")]
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)
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;; Reload patterns for AdvSIMD register list operands.
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(define_expand "mov<mode>"
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@ -8687,6 +8687,14 @@ aarch64_simd_attr_length_move (rtx_insn *insn)
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return 4;
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}
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/* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
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one of VSTRUCT modes: OI, CI, EI, or XI. */
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int
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aarch64_simd_attr_length_rglist (enum machine_mode mode)
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{
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return (GET_MODE_SIZE (mode) / UNITS_PER_VREG) * 4;
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}
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/* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
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alignment of a vector to 128 bits. */
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static HOST_WIDE_INT
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@ -10215,6 +10223,27 @@ aarch64_cannot_change_mode_class (machine_mode from,
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return true;
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}
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rtx
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aarch64_reverse_mask (enum machine_mode mode)
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{
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/* We have to reverse each vector because we dont have
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a permuted load that can reverse-load according to ABI rules. */
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rtx mask;
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rtvec v = rtvec_alloc (16);
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int i, j;
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int nunits = GET_MODE_NUNITS (mode);
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int usize = GET_MODE_UNIT_SIZE (mode);
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gcc_assert (BYTES_BIG_ENDIAN);
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gcc_assert (AARCH64_VALID_SIMD_QREG_MODE (mode));
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for (i = 0; i < nunits; i++)
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for (j = 0; j < usize; j++)
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RTVEC_ELT (v, i * usize + j) = GEN_INT ((i + 1) * usize - 1 - j);
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mask = gen_rtx_CONST_VECTOR (V16QImode, v);
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return force_reg (V16QImode, mask);
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}
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/* Implement MODES_TIEABLE_P. */
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bool
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@ -276,6 +276,7 @@
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UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
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UNSPEC_PMULL ; Used in aarch64-simd.md.
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UNSPEC_PMULL2 ; Used in aarch64-simd.md.
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UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
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])
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;; -------------------------------------------------------------------
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@ -652,6 +653,8 @@
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(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
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(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
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(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
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;; -------------------------------------------------------------------
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;; Code Iterators
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;; -------------------------------------------------------------------
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