constraints.md (ZR): New constraint.
2012-06-19 Tom de Vries <vries@codesourcery.com>
Maxim Kuvyrkov <maxim@codesourcery.com>
* config/mips/constraints.md (ZR): New constraint.
* config/mips/predicates.md (mem_noofs_operand): New predicate.
* config/mips/mips.c (mips_print_operand): Handle new print modifier.
* config/mips/mips.h (TARGET_XLP): Define.
(TARGET_SYNC_AFTER_SC): Update.
(ISA_HAS_SWAP, ISA_HAS_LDADD): Define.
* config/mips/sync.md (atomic_exchange, atomic_fetch_add): Use
XLP-specific swap and ldadd patterns.
(atomic_exchange_swap, atomic_fetch_add_ldadd): New patterns.
Co-Authored-By: Maxim Kuvyrkov <maxim@codesourcery.com>
From-SVN: r188804
This commit is contained in:
Tom de Vries
Maxim Kuvyrkov
parent
01c196ea91
commit
6399761a4a
6 changed files with 90 additions and 6 deletions
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@ -1,3 +1,16 @@
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2012-06-19 Tom de Vries <vries@codesourcery.com>
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Maxim Kuvyrkov <maxim@codesourcery.com>
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* config/mips/constraints.md (ZR): New constraint.
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* config/mips/predicates.md (mem_noofs_operand): New predicate.
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* config/mips/mips.c (mips_print_operand): Handle new print modifier.
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* config/mips/mips.h (TARGET_XLP): Define.
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(TARGET_SYNC_AFTER_SC): Update.
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(ISA_HAS_SWAP, ISA_HAS_LDADD): Define.
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* config/mips/sync.md (atomic_exchange, atomic_fetch_add): Use
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XLP-specific swap and ldadd patterns.
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(atomic_exchange_swap, atomic_fetch_add_ldadd): New patterns.
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2012-06-19 Tom de Vries <vries@codesourcery.com>
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Maxim Kuvyrkov <maxim@codesourcery.com>
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@ -231,3 +231,8 @@
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(define_constraint "Yx"
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"@internal"
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(match_operand 0 "low_bitmask_operand"))
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(define_memory_constraint "ZR"
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"@internal
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An address valid for loading/storing register exclusive"
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(match_operand 0 "mem_noofs_operand"))
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@ -7806,7 +7806,8 @@ mips_print_operand_punct_valid_p (unsigned char code)
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'D' Print the second part of a double-word register or memory operand.
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'L' Print the low-order register in a double-word register operand.
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'M' Print high-order register in a double-word register operand.
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'z' Print $0 if OP is zero, otherwise print OP normally. */
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'z' Print $0 if OP is zero, otherwise print OP normally.
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'b' Print the address of a memory operand, without offset. */
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static void
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mips_print_operand (FILE *file, rtx op, int letter)
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@ -7935,6 +7936,11 @@ mips_print_operand (FILE *file, rtx op, int letter)
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case MEM:
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if (letter == 'D')
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output_address (plus_constant (Pmode, XEXP (op, 0), 4));
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else if (letter == 'b')
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{
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gcc_assert (REG_P (XEXP (op, 0)));
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mips_print_operand (file, XEXP (op, 0), 0);
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}
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else if (letter && letter != 'z')
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output_operand_lossage ("invalid use of '%%%c'", letter);
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else
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@ -223,6 +223,7 @@ struct mips_cpu_info {
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#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
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|| mips_arch == PROCESSOR_SB1A)
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#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
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#define TARGET_XLP (mips_arch == PROCESSOR_XLP)
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/* Scheduling target defines. */
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#define TUNE_20KC (mips_tune == PROCESSOR_20KC)
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@ -311,7 +312,7 @@ struct mips_cpu_info {
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stores. It does not tell anything about ordering of loads and
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stores prior to and following the SC, only about the SC itself and
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those loads and stores follow it. */
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#define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
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#define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
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/* Define preprocessor macros for the -march and -mtune options.
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PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
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@ -1054,6 +1055,9 @@ struct mips_cpu_info {
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? TARGET_LLSC && !TARGET_MIPS16 \
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: ISA_HAS_LL_SC)
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#define ISA_HAS_SWAP (TARGET_XLP)
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#define ISA_HAS_LDADD (TARGET_XLP)
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/* ISA includes the baddu instruction. */
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#define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
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@ -370,3 +370,7 @@
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(define_predicate "small_data_pattern"
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(and (match_code "set,parallel,unspec,unspec_volatile,prefetch")
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(match_test "mips_small_data_pattern_p (op)")))
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(define_predicate "mem_noofs_operand"
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(and (match_code "mem")
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(match_code "reg" "0")))
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@ -607,8 +607,22 @@
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(match_operand:GPR 1 "memory_operand")
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(match_operand:GPR 2 "arith_operand")
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(match_operand:SI 3 "const_int_operand")]
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"GENERATE_LL_SC"
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"GENERATE_LL_SC || ISA_HAS_SWAP"
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{
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if (ISA_HAS_SWAP)
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{
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if (!mem_noofs_operand (operands[1], <MODE>mode))
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{
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rtx addr;
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addr = force_reg (Pmode, XEXP (operands[1], 0));
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operands[1] = replace_equiv_address (operands[1], addr);
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}
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operands[2] = force_reg (<MODE>mode, operands[2]);
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emit_insn (gen_atomic_exchange<mode>_swap (operands[0], operands[1],
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operands[2]));
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}
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else
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emit_insn (gen_atomic_exchange<mode>_llsc (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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@ -623,7 +637,7 @@
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UNSPEC_ATOMIC_EXCHANGE))
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(unspec_volatile:GPR [(match_operand:SI 3 "const_int_operand")]
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UNSPEC_ATOMIC_EXCHANGE)]
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"GENERATE_LL_SC"
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"GENERATE_LL_SC && !ISA_HAS_SWAP"
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{ return mips_output_sync_loop (insn, operands); }
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[(set_attr "sync_insn1" "li,move")
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(set_attr "sync_oldval" "0")
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@ -631,13 +645,38 @@
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(set_attr "sync_insn1_op2" "2")
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(set_attr "sync_memmodel" "3")])
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;; XLP issues implicit sync for SWAP/LDADD, so no need for an explicit one.
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(define_insn "atomic_exchange<mode>_swap"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(unspec_volatile:GPR [(match_operand:GPR 1 "mem_noofs_operand" "+ZR")]
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UNSPEC_ATOMIC_EXCHANGE))
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(set (match_dup 1)
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(unspec_volatile:GPR [(match_operand:GPR 2 "register_operand" "0")]
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UNSPEC_ATOMIC_EXCHANGE))]
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"ISA_HAS_SWAP"
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"swap<size>\t%0,%b1")
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(define_expand "atomic_fetch_add<mode>"
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[(match_operand:GPR 0 "register_operand")
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(match_operand:GPR 1 "memory_operand")
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(match_operand:GPR 2 "arith_operand")
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(match_operand:SI 3 "const_int_operand")]
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"GENERATE_LL_SC"
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"GENERATE_LL_SC || ISA_HAS_LDADD"
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{
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if (ISA_HAS_LDADD)
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{
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if (!mem_noofs_operand (operands[1], <MODE>mode))
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{
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rtx addr;
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addr = force_reg (Pmode, XEXP (operands[1], 0));
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operands[1] = replace_equiv_address (operands[1], addr);
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}
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operands[2] = force_reg (<MODE>mode, operands[2]);
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emit_insn (gen_atomic_fetch_add<mode>_ldadd (operands[0], operands[1],
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operands[2]));
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}
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else
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emit_insn (gen_atomic_fetch_add<mode>_llsc (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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@ -654,10 +693,23 @@
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UNSPEC_ATOMIC_FETCH_OP))
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(unspec_volatile:GPR [(match_operand:SI 3 "const_int_operand")]
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UNSPEC_ATOMIC_FETCH_OP)]
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"GENERATE_LL_SC"
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"GENERATE_LL_SC && !ISA_HAS_LDADD"
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{ return mips_output_sync_loop (insn, operands); }
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[(set_attr "sync_insn1" "addiu,addu")
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(set_attr "sync_oldval" "0")
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(set_attr "sync_mem" "1")
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(set_attr "sync_insn1_op2" "2")
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(set_attr "sync_memmodel" "3")])
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;; XLP issues implicit sync for SWAP/LDADD, so no need for an explicit one.
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(define_insn "atomic_fetch_add<mode>_ldadd"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(unspec_volatile:GPR [(match_operand:GPR 1 "mem_noofs_operand" "+ZR")]
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UNSPEC_ATOMIC_FETCH_OP))
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(set (match_dup 1)
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(unspec_volatile:GPR
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[(plus:GPR (match_dup 1)
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(match_operand:GPR 2 "register_operand" "0"))]
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UNSPEC_ATOMIC_FETCH_OP))]
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"ISA_HAS_LDADD"
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"ldadd<size>\t%0,%b1")
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