RISC-V: Support highpart overlap for vext.vf
PR target/112431 gcc/ChangeLog: * config/riscv/vector.md: Support highpart overlap for vext.vf2 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/unop_v_constraint-2.c: Adapt test. * gcc.target/riscv/rvv/base/pr112431-4.c: New test. * gcc.target/riscv/rvv/base/pr112431-5.c: New test. * gcc.target/riscv/rvv/base/pr112431-6.c: New test.
This commit is contained in:
Juzhe-Zhong
Pan Li
parent
31d8cf17ca
commit
62685890d8
5 changed files with 234 additions and 10 deletions
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@ -3683,23 +3683,24 @@
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;; Vector Double-Widening Sign-extend and Zero-extend.
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(define_insn "@pred_<optab><mode>_vf2"
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[(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
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[(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
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(if_then_else:VWEXTI
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
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(match_operand 4 "vector_length_operand" " rK, rK")
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(match_operand 5 "const_int_operand" " i, i")
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(match_operand 6 "const_int_operand" " i, i")
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(match_operand 7 "const_int_operand" " i, i")
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[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
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(match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
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(match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
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(match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(any_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
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(match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
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(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
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(match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
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"TARGET_VECTOR"
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"v<sz>ext.vf2\t%0,%3%p1"
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[(set_attr "type" "vext")
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(set_attr "mode" "<MODE>")])
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(set_attr "mode" "<MODE>")
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(set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")])
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;; Vector Quad-Widening Sign-extend and Zero-extend.
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(define_insn "@pred_<optab><mode>_vf4"
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104
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c
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104
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c
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@ -0,0 +1,104 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
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#include "riscv_vector.h"
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size_t __attribute__ ((noinline))
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sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
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size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,
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size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,
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size_t sum15)
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{
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return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9
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+ sum10 + sum11 + sum12 + sum13 + sum14 + sum15;
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}
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size_t
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foo (char const *buf, size_t len)
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{
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size_t sum = 0;
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size_t vl = __riscv_vsetvlmax_e8m8 ();
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size_t step = vl * 4;
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const char *it = buf, *end = buf + len;
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for (; it + step <= end;)
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{
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vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl);
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it += vl;
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asm volatile("nop" ::: "memory");
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vint16m2_t vw0 = __riscv_vsext_vf2_i16m2 (v0, vl);
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vint16m2_t vw1 = __riscv_vsext_vf2_i16m2 (v1, vl);
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vint16m2_t vw2 = __riscv_vsext_vf2_i16m2 (v2, vl);
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vint16m2_t vw3 = __riscv_vsext_vf2_i16m2 (v3, vl);
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vint16m2_t vw4 = __riscv_vsext_vf2_i16m2 (v4, vl);
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vint16m2_t vw5 = __riscv_vsext_vf2_i16m2 (v5, vl);
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vint16m2_t vw6 = __riscv_vsext_vf2_i16m2 (v6, vl);
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vint16m2_t vw7 = __riscv_vsext_vf2_i16m2 (v7, vl);
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vint16m2_t vw8 = __riscv_vsext_vf2_i16m2 (v8, vl);
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vint16m2_t vw9 = __riscv_vsext_vf2_i16m2 (v9, vl);
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vint16m2_t vw10 = __riscv_vsext_vf2_i16m2 (v10, vl);
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vint16m2_t vw11 = __riscv_vsext_vf2_i16m2 (v11, vl);
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vint16m2_t vw12 = __riscv_vsext_vf2_i16m2 (v12, vl);
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vint16m2_t vw13 = __riscv_vsext_vf2_i16m2 (v13, vl);
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vint16m2_t vw14 = __riscv_vsext_vf2_i16m2 (v14, vl);
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vint16m2_t vw15 = __riscv_vsext_vf2_i16m2 (v15, vl);
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asm volatile("nop" ::: "memory");
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size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0);
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size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1);
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size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2);
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size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3);
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size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4);
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size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5);
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size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6);
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size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7);
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size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8);
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size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9);
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size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10);
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size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11);
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size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12);
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size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13);
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size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14);
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size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15);
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sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8,
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sum9, sum10, sum11, sum12, sum13, sum14, sum15);
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}
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return sum;
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}
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/* { dg-final { scan-assembler-not {vmv1r} } } */
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/* { dg-final { scan-assembler-not {vmv2r} } } */
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/* { dg-final { scan-assembler-not {vmv4r} } } */
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/* { dg-final { scan-assembler-not {vmv8r} } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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68
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-5.c
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68
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-5.c
Normal file
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@ -0,0 +1,68 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
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#include "riscv_vector.h"
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size_t __attribute__ ((noinline))
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sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
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size_t sum5, size_t sum6, size_t sum7)
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{
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return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7;
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}
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size_t
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foo (char const *buf, size_t len)
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{
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size_t sum = 0;
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size_t vl = __riscv_vsetvlmax_e8m8 ();
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size_t step = vl * 4;
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const char *it = buf, *end = buf + len;
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for (; it + step <= end;)
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{
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vint8m2_t v0 = __riscv_vle8_v_i8m2 ((void *) it, vl);
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it += vl;
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vint8m2_t v1 = __riscv_vle8_v_i8m2 ((void *) it, vl);
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it += vl;
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vint8m2_t v2 = __riscv_vle8_v_i8m2 ((void *) it, vl);
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it += vl;
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vint8m2_t v3 = __riscv_vle8_v_i8m2 ((void *) it, vl);
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it += vl;
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vint8m2_t v4 = __riscv_vle8_v_i8m2 ((void *) it, vl);
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it += vl;
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vint8m2_t v5 = __riscv_vle8_v_i8m2 ((void *) it, vl);
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it += vl;
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vint8m2_t v6 = __riscv_vle8_v_i8m2 ((void *) it, vl);
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it += vl;
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vint8m2_t v7 = __riscv_vle8_v_i8m2 ((void *) it, vl);
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it += vl;
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asm volatile("nop" ::: "memory");
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vint16m4_t vw0 = __riscv_vsext_vf2_i16m4 (v0, vl);
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vint16m4_t vw1 = __riscv_vsext_vf2_i16m4 (v1, vl);
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vint16m4_t vw2 = __riscv_vsext_vf2_i16m4 (v2, vl);
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vint16m4_t vw3 = __riscv_vsext_vf2_i16m4 (v3, vl);
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vint16m4_t vw4 = __riscv_vsext_vf2_i16m4 (v4, vl);
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vint16m4_t vw5 = __riscv_vsext_vf2_i16m4 (v5, vl);
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vint16m4_t vw6 = __riscv_vsext_vf2_i16m4 (v6, vl);
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vint16m4_t vw7 = __riscv_vsext_vf2_i16m4 (v7, vl);
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asm volatile("nop" ::: "memory");
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size_t sum0 = __riscv_vmv_x_s_i16m4_i16 (vw0);
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size_t sum1 = __riscv_vmv_x_s_i16m4_i16 (vw1);
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size_t sum2 = __riscv_vmv_x_s_i16m4_i16 (vw2);
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size_t sum3 = __riscv_vmv_x_s_i16m4_i16 (vw3);
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size_t sum4 = __riscv_vmv_x_s_i16m4_i16 (vw4);
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size_t sum5 = __riscv_vmv_x_s_i16m4_i16 (vw5);
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size_t sum6 = __riscv_vmv_x_s_i16m4_i16 (vw6);
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size_t sum7 = __riscv_vmv_x_s_i16m4_i16 (vw7);
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sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7);
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}
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return sum;
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}
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/* { dg-final { scan-assembler-not {vmv1r} } } */
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/* { dg-final { scan-assembler-not {vmv2r} } } */
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/* { dg-final { scan-assembler-not {vmv4r} } } */
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/* { dg-final { scan-assembler-not {vmv8r} } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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51
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-6.c
Normal file
51
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-6.c
Normal file
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@ -0,0 +1,51 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
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#include "riscv_vector.h"
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size_t __attribute__ ((noinline))
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sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3)
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{
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return sum0 + sum1 + sum2 + sum3;
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}
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size_t
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foo (char const *buf, size_t len)
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{
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size_t sum = 0;
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size_t vl = __riscv_vsetvlmax_e8m8 ();
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size_t step = vl * 4;
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const char *it = buf, *end = buf + len;
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for (; it + step <= end;)
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{
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vint8m4_t v0 = __riscv_vle8_v_i8m4 ((void *) it, vl);
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it += vl;
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vint8m4_t v1 = __riscv_vle8_v_i8m4 ((void *) it, vl);
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it += vl;
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vint8m4_t v2 = __riscv_vle8_v_i8m4 ((void *) it, vl);
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it += vl;
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vint8m4_t v3 = __riscv_vle8_v_i8m4 ((void *) it, vl);
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it += vl;
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asm volatile("nop" ::: "memory");
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vint16m8_t vw0 = __riscv_vsext_vf2_i16m8 (v0, vl);
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vint16m8_t vw1 = __riscv_vsext_vf2_i16m8 (v1, vl);
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vint16m8_t vw2 = __riscv_vsext_vf2_i16m8 (v2, vl);
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vint16m8_t vw3 = __riscv_vsext_vf2_i16m8 (v3, vl);
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asm volatile("nop" ::: "memory");
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size_t sum0 = __riscv_vmv_x_s_i16m8_i16 (vw0);
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size_t sum1 = __riscv_vmv_x_s_i16m8_i16 (vw1);
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size_t sum2 = __riscv_vmv_x_s_i16m8_i16 (vw2);
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size_t sum3 = __riscv_vmv_x_s_i16m8_i16 (vw3);
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sum += sumation (sum0, sum1, sum2, sum3);
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}
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return sum;
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}
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/* { dg-final { scan-assembler-not {vmv1r} } } */
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/* { dg-final { scan-assembler-not {vmv2r} } } */
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/* { dg-final { scan-assembler-not {vmv4r} } } */
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/* { dg-final { scan-assembler-not {vmv8r} } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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@ -30,7 +30,7 @@ void f1 (void * in, void *out)
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** vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
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** vsext\.vf2\tv[0-9]+,\s*v[0-9]+
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** ...
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** vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
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** vsext\.vf2\tv[0-9]+,\s*v[0-9]+,\s*v0.t
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** vse64\.v\tv[0-9]+,0\([a-x0-9]+\)
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** ret
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*/
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