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mips.h (PROCESSOR_R7000): New processor_type.

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* config/mips/mips.h (PROCESSOR_R7000): New processor_type.
	(TARGET_MIPS7000, TUNE_MIPS7000): New macros.
	(GENERATE_MULT3_SI): True for TARGET_MIPS7000.
	* config/mips/mips.c (mips_cpu_info_table): Add rm7000 entry.
	(mips_rtx_costs): Adjust integer multiplication costs for the rm7000.
	(mips_issue_rate): Handle PROCESSOR_R7000.
	(mips_use_dfa_pipeline_interface): Likewise.
	* config/mips/7000.md: New file.
	* config/mips/mips.md: Include it.
	(define_attr cpu): Add r7000.
	(mulsi3_mult3): Use "mul" for rm7000 code.

From-SVN: r69394
This commit is contained in:
Stan Cox 2003-07-15 08:34:54 +00:00 • committed by Richard Sandiford
parent 5a2515e667
commit 5fe25f470b
5 changed files with 237 additions and 1 deletions
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14
gcc/ChangeLog
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@ -1,3 +1,17 @@
2003-07-15 Stan Cox <scox@redhat.com>
* config/mips/mips.h (PROCESSOR_R7000): New processor_type.
(TARGET_MIPS7000, TUNE_MIPS7000): New macros.
(GENERATE_MULT3_SI): True for TARGET_MIPS7000.
* config/mips/mips.c (mips_cpu_info_table): Add rm7000 entry.
(mips_rtx_costs): Adjust integer multiplication costs for the rm7000.
(mips_issue_rate): Handle PROCESSOR_R7000.
(mips_use_dfa_pipeline_interface): Likewise.
* config/mips/7000.md: New file.
* config/mips/mips.md: Include it.
(define_attr cpu): Add r7000.
(mulsi3_mult3): Use "mul" for rm7000 code.
2003-07-15 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (define_attr type): Add condmove. Use it for

211
gcc/config/mips/7000.md Normal file
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@ -0,0 +1,211 @@
;; DFA-based pipeline description for the RM7000.
;; Copyright (C) 2003 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 2, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING. If not, write to the
;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
;; MA 02111-1307, USA.
;; .........................
;;
;; The RM7000 is a dual-issue processor that can bundle instructions as:
;; {arith|load|store}{arith|imul|idiv|branch|float}
;;
;; Reference:
;; "RM7000 Family User Manual, PMC-2002296"
;;
;; .........................
;; Use three automata to isolate long latency operations, reducing space.
(define_automaton "rm7000_other, rm7000_fdiv, rm7000_idiv")
;;
;; Describe the resources.
;;
;; Global
(define_cpu_unit "rm7_iss0,rm7_iss1" "rm7000_other")
;; Integer execution unit (M-Pipe).
(define_cpu_unit "ixum_addsub_agen" "rm7000_other")
;; Integer execution unit (F-Pipe).
(define_cpu_unit "ixuf_addsub" "rm7000_other")
(define_cpu_unit "ixuf_branch" "rm7000_other")
(define_cpu_unit "ixuf_mpydiv" "rm7000_other")
(define_cpu_unit "ixuf_mpydiv_iter" "rm7000_idiv")
;; Floating-point unit (F-Pipe).
(define_cpu_unit "fxuf_add" "rm7000_other")
(define_cpu_unit "fxuf_mpy" "rm7000_other")
(define_cpu_unit "fxuf_mpy_iter" "rm7000_fdiv")
(define_cpu_unit "fxuf_divsqrt" "rm7000_other")
(define_cpu_unit "fxuf_divsqrt_iter" "rm7000_fdiv")
(exclusion_set "ixuf_addsub"
"ixuf_branch,ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
(exclusion_set "ixuf_branch" "ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
(exclusion_set "ixuf_mpydiv" "fxuf_add,fxuf_mpy,fxuf_divsqrt")
(exclusion_set "fxuf_add" "fxuf_mpy,fxuf_divsqrt")
(exclusion_set "fxuf_mpy" "fxuf_divsqrt")
;; After branch any insn can not be issued.
(absence_set "rm7_iss0,rm7_iss1" "ixuf_branch")
;;
;; Define reservations for unit name mnemonics or combinations.
;;
(define_reservation "rm7_iss" "rm7_iss0|rm7_iss1")
(define_reservation "rm7_single_dispatch" "rm7_iss0+rm7_iss1")
(define_reservation "rm7_iaddsub" "rm7_iss+(ixum_addsub_agen|ixuf_addsub)")
(define_reservation "rm7_imem" "rm7_iss+ixum_addsub_agen")
(define_reservation "rm7_impydiv" "rm7_iss+ixuf_mpydiv")
(define_reservation "rm7_impydiv_iter" "ixuf_mpydiv_iter")
(define_reservation "rm7_branch" "rm7_iss+ixuf_branch")
(define_reservation "rm7_fpadd" "rm7_iss+fxuf_add")
(define_reservation "rm7_fpmpy" "rm7_iss+fxuf_mpy")
(define_reservation "rm7_fpmpy_iter" "fxuf_mpy_iter")
(define_reservation "rm7_fpdivsqr" "rm7_iss+fxuf_divsqrt")
(define_reservation "rm7_fpdivsqr_iter" "fxuf_divsqrt_iter")
;;
;; Describe instruction reservations for integer operations.
;;
(define_insn_reservation "rm7_int_other" 1
(and (eq_attr "cpu" "r7000")
(eq_attr "type" "arith,darith,const,move,condmove,icmp,nop"))
"rm7_iaddsub")
(define_insn_reservation "rm7_ld" 2 (and (eq_attr "cpu" "r7000")
(eq_attr "type" "load"))
"rm7_imem")
(define_insn_reservation "rm7_st" 1 (and (eq_attr "cpu" "r7000")
(eq_attr "type" "store"))
"rm7_imem")
(define_insn_reservation "rm7_idiv_si" 36 (and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "SI")))
"rm7_impydiv+(rm7_impydiv_iter*36)")
(define_insn_reservation "rm7_idiv_di" 68 (and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "DI")))
"rm7_impydiv+(rm7_impydiv_iter*68)")
(define_insn_reservation "rm7_impy_si_mult" 5
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "imul,imadd")
(and (eq_attr "mode" "SI")
(match_operand 0 "hilo_operand" ""))))
"rm7_impydiv+(rm7_impydiv_iter*3)")
;; There are an additional 2 stall cycles.
(define_insn_reservation "rm7_impy_si_mul" 2
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "imul,imadd")
(and (eq_attr "mode" "SI")
(not (match_operand 0 "hilo_operand" "")))))
"rm7_impydiv")
(define_insn_reservation "rm7_impy_di" 9 (and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "imul")
(eq_attr "mode" "DI")))
"rm7_impydiv+(rm7_impydiv_iter*8)")
;; Move to/from HI/LO.
(define_insn_reservation "rm7_mthilo" 3
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "hilo")
(match_operand 0 "hilo_operand" "")))
"rm7_impydiv")
(define_insn_reservation "rm7_mfhilo" 1
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "hilo")
(not (match_operand 0 "hilo_operand" ""))))
"rm7_impydiv")
;; Move to/from fp coprocessor.
(define_insn_reservation "rm7_ixfer" 2 (and (eq_attr "cpu" "r7000")
(eq_attr "type" "xfer"))
"rm7_iaddsub")
(define_insn_reservation "rm7_ibr" 3 (and (eq_attr "cpu" "r7000")
(eq_attr "type" "branch,jump,call"))
"rm7_branch")
;;
;; Describe instruction reservations for the floating-point operations.
;;
(define_insn_reservation "rm7_fp_quick" 4
(and (eq_attr "cpu" "r7000")
(eq_attr "type" "fneg,fcmp,fabs"))
"rm7_fpadd")
(define_insn_reservation "rm7_fp_other" 4
(and (eq_attr "cpu" "r7000")
(eq_attr "type" "fadd"))
"rm7_fpadd")
(define_insn_reservation "rm7_fp_cvt" 4
(and (eq_attr "cpu" "r7000")
(eq_attr "type" "fcvt"))
"rm7_fpadd")
(define_insn_reservation "rm7_fp_divsqrt_df" 36
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
"rm7_fpdivsqr+(rm7_fpdivsqr_iter*36)")
(define_insn_reservation "rm7_fp_divsqrt_sf" 21
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "SF")))
"rm7_fpdivsqr+(rm7_fpdivsqr_iter*21)")
(define_insn_reservation "rm7_fp_rsqrt_df" 68
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
"rm7_fpdivsqr+(rm7_fpdivsqr_iter*68)")
(define_insn_reservation "rm7_fp_rsqrt_sf" 38
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "SF")))
"rm7_fpdivsqr+(rm7_fpdivsqr_iter*38)")
(define_insn_reservation "rm7_fp_mpy_sf" 4
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
"rm7_fpmpy+rm7_fpmpy_iter")
(define_insn_reservation "rm7_fp_mpy_df" 5
(and (eq_attr "cpu" "r7000")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
"rm7_fpmpy+(rm7_fpmpy_iter*2)")
;; Force single-dispatch for unknown or multi.
(define_insn_reservation "rm7_unknown" 1 (and (eq_attr "cpu" "r7000")
(eq_attr "type" "unknown,multi"))
"rm7_single_dispatch")

5
gcc/config/mips/mips.c
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@ -807,6 +807,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
{ "vr5000", PROCESSOR_R5000, 4 },
{ "vr5400", PROCESSOR_R5400, 4 },
{ "vr5500", PROCESSOR_R5500, 4 },
{ "rm7000", PROCESSOR_R7000, 4 },
/* MIPS32 */
{ "4kc", PROCESSOR_4KC, 32 },
@ -2661,6 +2662,8 @@ mips_rtx_costs (x, code, outer_code, total)
*total = COSTS_N_INSNS (2);
else if (TUNE_MIPS5400 || TUNE_MIPS5500)
*total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
else if (TUNE_MIPS7000)
*total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
else if (TUNE_MIPS6000)
*total = COSTS_N_INSNS (17);
else if (TUNE_MIPS5000)
@ -10261,6 +10264,7 @@ mips_issue_rate ()
case PROCESSOR_R3000: return 1;
case PROCESSOR_R5400: return 2;
case PROCESSOR_R5500: return 2;
case PROCESSOR_R7000: return 2;
default:
return 1;
@ -10280,6 +10284,7 @@ mips_use_dfa_pipeline_interface ()
{
case PROCESSOR_R5400:
case PROCESSOR_R5500:
case PROCESSOR_R7000:
case PROCESSOR_SR71000:
return true;

4
gcc/config/mips/mips.h
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@ -65,6 +65,7 @@ enum processor_type {
PROCESSOR_R5000,
PROCESSOR_R5400,
PROCESSOR_R5500,
PROCESSOR_R7000,
PROCESSOR_R8000,
PROCESSOR_SB1,
PROCESSOR_SR71000
@ -329,6 +330,7 @@ extern const struct mips_cpu_info *mips_tune_info;
#define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
@ -340,6 +342,7 @@ extern const struct mips_cpu_info *mips_tune_info;
#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
#define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
@ -762,6 +765,7 @@ extern const struct mips_cpu_info *mips_tune_info;
#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_MIPS7000 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \

4
gcc/config/mips/mips.md
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@ -195,7 +195,7 @@
;; ??? Fix everything that tests this attribute.
(define_attr "cpu"
"default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r8000,sb1,sr71000"
"default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,sb1,sr71000"
(const (symbol_ref "mips_cpu_attr")))
;; The type of hardware hazard associated with this instruction.
@ -623,6 +623,7 @@
(include "5400.md")
(include "5500.md")
(include "7000.md")
(include "sr71k.md")
@ -1496,6 +1497,7 @@
if (TARGET_MAD
|| TARGET_MIPS5400
|| TARGET_MIPS5500
|| TARGET_MIPS7000
|| ISA_MIPS32
|| ISA_MIPS32R2
|| ISA_MIPS64)