invoke.texi: Document --fix-cortex-m3.
2008-11-13 Paul Brook <paul@codesourcery.com> gcc/ * doc/invoke.texi: Document --fix-cortex-m3. * config/arm/arm.c (arm_override_options): Set fix_cm3_ldrd if Cortex-M3 cpu is selected. (output_move_double): Avoid overlapping base register and first destination register when fix_cm3_ldrd. * config/arm/arm.opt: Add mfix-cortex-m3-ldrd. From-SVN: r141822
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Paul Brook
Paul Brook
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4 changed files with 74 additions and 24 deletions
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@ -1,3 +1,12 @@
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2008-11-13 Paul Brook <paul@codesourcery.com>
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* doc/invoke.texi: Document --fix-cortex-m3.
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* config/arm/arm.c (arm_override_options): Set fix_cm3_ldrd if
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Cortex-M3 cpu is selected.
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(output_move_double): Avoid overlapping base register and first
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destination register when fix_cm3_ldrd.
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* config/arm/arm.opt: Add mfix-cortex-m3-ldrd.
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2008-11-13 Jakub Jelinek <jakub@redhat.com>
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PR bootstrap/38100
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@ -1037,6 +1037,7 @@ arm_override_options (void)
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{
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unsigned i;
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enum processor_type target_arch_cpu = arm_none;
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enum processor_type selected_cpu = arm_none;
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/* Set up the flags based on the cpu/architecture selected by the user. */
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for (i = ARRAY_SIZE (arm_select); i--;)
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@ -1069,6 +1070,9 @@ arm_override_options (void)
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if (i == ARM_OPT_SET_ARCH)
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target_arch_cpu = sel->core;
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if (i == ARM_OPT_SET_CPU)
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selected_cpu = (enum processor_type) (sel - ptr->processors);
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if (i != ARM_OPT_SET_TUNE)
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{
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/* If we have been given an architecture and a processor
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@ -1099,21 +1103,20 @@ arm_override_options (void)
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{
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const struct processors * sel;
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unsigned int sought;
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enum processor_type cpu;
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cpu = TARGET_CPU_DEFAULT;
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if (cpu == arm_none)
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selected_cpu = TARGET_CPU_DEFAULT;
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if (selected_cpu == arm_none)
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{
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#ifdef SUBTARGET_CPU_DEFAULT
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/* Use the subtarget default CPU if none was specified by
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configure. */
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cpu = SUBTARGET_CPU_DEFAULT;
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selected_cpu = SUBTARGET_CPU_DEFAULT;
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#endif
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/* Default to ARM6. */
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if (cpu == arm_none)
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cpu = arm6;
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if (selected_cpu == arm_none)
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selected_cpu = arm6;
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}
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sel = &all_cores[cpu];
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sel = &all_cores[selected_cpu];
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insn_flags = sel->flags;
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@ -1505,6 +1508,15 @@ arm_override_options (void)
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arm_pic_register = pic_register;
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}
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/* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
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if (fix_cm3_ldrd == 2)
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{
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if (selected_cpu == cortexm3)
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fix_cm3_ldrd = 1;
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else
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fix_cm3_ldrd = 0;
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}
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/* ??? We might want scheduling for thumb2. */
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if (TARGET_THUMB && flag_schedule_insns)
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{
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@ -9978,7 +9990,8 @@ output_move_double (rtx *operands)
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switch (GET_CODE (XEXP (operands[1], 0)))
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{
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case REG:
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if (TARGET_LDRD)
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if (TARGET_LDRD
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&& !(fix_cm3_ldrd && reg0 == REGNO(XEXP (operands[1], 0))))
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output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands);
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else
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output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
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@ -10010,6 +10023,10 @@ output_move_double (rtx *operands)
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case PRE_MODIFY:
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case POST_MODIFY:
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/* Autoicrement addressing modes should never have overlapping
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base and destination registers, and overlapping index registers
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are already prohibited, so this doesn't need to worry about
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fix_cm3_ldrd. */
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otherops[0] = operands[0];
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otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
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otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
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@ -10062,11 +10079,15 @@ output_move_double (rtx *operands)
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/* We might be able to use ldrd %0, %1 here. However the range is
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different to ldr/adr, and it is broken on some ARMv7-M
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implementations. */
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output_asm_insn ("adr%?\t%0, %1", operands);
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/* Use the second register of the pair to avoid problematic
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overlap. */
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otherops[1] = operands[1];
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output_asm_insn ("adr%?\t%0, %1", otherops);
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operands[1] = otherops[0];
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if (TARGET_LDRD)
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output_asm_insn ("ldr%(d%)\t%0, [%0]", operands);
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output_asm_insn ("ldr%(d%)\t%0, [%1]", operands);
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else
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output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
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output_asm_insn ("ldm%(ia%)\t%1, %M0", operands);
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break;
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/* ??? This needs checking for thumb2. */
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@ -10099,30 +10120,37 @@ output_move_double (rtx *operands)
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return "";
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}
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}
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otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1);
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operands[1] = otherops[0];
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if (TARGET_LDRD
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&& (GET_CODE (otherops[2]) == REG
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|| (GET_CODE (otherops[2]) == CONST_INT
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&& INTVAL (otherops[2]) > -256
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&& INTVAL (otherops[2]) < 256)))
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{
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if (reg_overlap_mentioned_p (otherops[0],
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if (reg_overlap_mentioned_p (operands[0],
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otherops[2]))
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{
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rtx tmp;
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/* Swap base and index registers over to
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avoid a conflict. */
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otherops[1] = XEXP (XEXP (operands[1], 0), 1);
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otherops[2] = XEXP (XEXP (operands[1], 0), 0);
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tmp = otherops[1];
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otherops[1] = otherops[2];
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otherops[2] = tmp;
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}
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/* If both registers conflict, it will usually
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have been fixed by a splitter. */
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if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
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if (reg_overlap_mentioned_p (operands[0], otherops[2])
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|| (fix_cm3_ldrd && reg0 == REGNO (otherops[1])))
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{
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output_asm_insn ("add%?\t%1, %1, %2", otherops);
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output_asm_insn ("ldr%(d%)\t%0, [%1]",
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otherops);
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output_asm_insn ("add%?\t%0, %1, %2", otherops);
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output_asm_insn ("ldr%(d%)\t%0, [%1]", operands);
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}
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else
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output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
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{
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otherops[0] = operands[0];
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output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
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}
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return "";
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}
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@ -10140,9 +10168,9 @@ output_move_double (rtx *operands)
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output_asm_insn ("sub%?\t%0, %1, %2", otherops);
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if (TARGET_LDRD)
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return "ldr%(d%)\t%0, [%0]";
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return "ldr%(d%)\t%0, [%1]";
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return "ldm%(ia%)\t%0, %M0";
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return "ldm%(ia%)\t%1, %M0";
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}
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else
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{
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@ -159,4 +159,9 @@ Use Neon quad-word (rather than double-word) registers for vectorization
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mword-relocations
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Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
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+Only generate absolute relocations on word sized values.
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Only generate absolute relocations on word sized values.
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mfix-cortex-m3-ldrd
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Target Report Var(fix_cm3_ldrd) Init(2)
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Avoid overlapping destination and address registers on LDRD instructions
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that may trigger Cortex-M3 errata.
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@ -452,8 +452,9 @@ Objective-C and Objective-C++ Dialects}.
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-mthumb -marm @gol
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-mtpcs-frame -mtpcs-leaf-frame @gol
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-mcaller-super-interworking -mcallee-super-interworking @gol
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-mtp=@var{name}
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-mword-relocations}
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-mtp=@var{name} @gol
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-mword-relocations @gol
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-mfix-cortex-m3-ldrd}
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@emph{AVR Options}
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@gccoptlist{-mmcu=@var{mcu} -msize -minit-stack=@var{n} -mno-interrupts @gol
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@ -8708,6 +8709,13 @@ Put functions, data, and readonly data in @var{text-section},
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by default. This can be overridden with the @code{section} attribute.
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@xref{Variable Attributes}.
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@item -mfix-cortex-m3-ldrd
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@opindex mfix-cortex-m3-ldrd
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Some Cortex-M3 cores can cause data corruption when @code{ldrd} instructions
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with overlapping destination and base registers are used. This option avoids
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generating these instructions. This option is enabled by default when
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@option{-mcpu=cortex-m3} is specified.
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@end table
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@node ARM Options
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