RISC-V: Add rounding mode operand for fixed-point patterns
Since we are going to have fixed-point intrinsics that are modeling rounding mode https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222 We should have operand to specify rounding mode in fixed-point instructions. We don't support these modeling rounding mode intrinsics yet but we will definetely support them later. This is the preparing patch for new coming intrinsics. gcc/ChangeLog: * config/riscv/riscv-protos.h (enum vxrm_field_enum): New enum. * config/riscv/riscv-vector-builtins.cc (function_expander::use_exact_insn): Add default rounding mode operand. * config/riscv/riscv.cc (riscv_hard_regno_nregs): Add VXRM_REGNUM. (riscv_hard_regno_mode_ok): Ditto. (riscv_conditional_register_usage): Ditto. * config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto. (VXRM_REG_P): Ditto. (RISCV_DWARF_VXRM): Ditto. * config/riscv/riscv.md: Ditto. * config/riscv/vector.md: Ditto Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
This commit is contained in:
Juzhe-Zhong
Pan Li
parent
47c4e96ad6
commit
5ed880788b
6 changed files with 77 additions and 23 deletions
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@ -223,6 +223,14 @@ machine_mode preferred_simd_mode (scalar_mode);
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opt_machine_mode get_mask_mode (machine_mode);
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void expand_vec_series (rtx, rtx, rtx);
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void expand_vec_init (rtx, rtx);
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/* Rounding mode bitfield for fixed point VXRM. */
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enum vxrm_field_enum
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{
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VXRM_RNU,
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VXRM_RNE,
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VXRM_RDN,
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VXRM_ROD
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};
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}
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/* We classify builtin types into two classes:
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@ -3288,6 +3288,13 @@ function_expander::use_exact_insn (insn_code icode)
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if (base->apply_vl_p ())
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add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
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/* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
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We add default rounding mode for the intrinsics that didn't model rounding
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mode yet. */
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if (opno != insn_data[icode].n_generator_args)
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add_input_operand (Pmode, const0_rtx);
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return generate_insn (icode);
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}
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@ -6082,7 +6082,7 @@ riscv_hard_regno_nregs (unsigned int regno, machine_mode mode)
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/* mode for VL or VTYPE are just a marker, not holding value,
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so it always consume one register. */
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if (regno == VTYPE_REGNUM || regno == VL_REGNUM)
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if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno))
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return 1;
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/* Assume every valid non-vector mode fits in one vector register. */
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@ -6150,7 +6150,7 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
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if (lmul != 1)
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return ((regno % lmul) == 0);
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}
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else if (regno == VL_REGNUM || regno == VTYPE_REGNUM)
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else if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno))
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return true;
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else
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return false;
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@ -6586,6 +6586,7 @@ riscv_conditional_register_usage (void)
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fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1;
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fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1;
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fixed_regs[VXRM_REGNUM] = call_used_regs[VXRM_REGNUM] = 1;
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}
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}
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@ -121,7 +121,8 @@ ASM_MISA_SPEC
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/* The mapping from gcc register number to DWARF 2 CFA column number. */
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#define DWARF_FRAME_REGNUM(REGNO) \
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(VL_REG_P (REGNO) ? RISCV_DWARF_VL \
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(VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM \
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: VL_REG_P (REGNO) ? RISCV_DWARF_VL \
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: VTYPE_REG_P (REGNO) \
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? RISCV_DWARF_VTYPE \
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: (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO) \
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@ -372,6 +373,7 @@ ASM_MISA_SPEC
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((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM)
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#define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM)
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#define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM)
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#define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM)
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/* True when REGNO is in SIBCALL_REGS set. */
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#define SIBCALL_REG_P(REGNO) \
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@ -390,6 +392,7 @@ ASM_MISA_SPEC
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#define FRAME_POINTER_REGNUM 65
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/* Define Dwarf for RVV. */
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#define RISCV_DWARF_VXRM (4096 + 0x00a)
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#define RISCV_DWARF_VL (4096 + 0xc20)
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#define RISCV_DWARF_VTYPE (4096 + 0xc21)
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#define RISCV_DWARF_VLENB (4096 + 0xc22)
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@ -135,6 +135,7 @@
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(EXCEPTION_RETURN 2)
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(VL_REGNUM 66)
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(VTYPE_REGNUM 67)
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(VXRM_REGNUM 68)
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])
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(include "predicates.md")
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@ -3317,8 +3317,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(any_sat_int_binop:VI
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(match_operand:VI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, vr, vr, vr, vr")
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(match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
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@ -3346,8 +3348,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(sat_int_plus_binop:VI_QHS
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(vec_duplicate:VI_QHS
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(match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
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@ -3367,8 +3371,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(sat_int_minus_binop:VI_QHS
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(match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
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(vec_duplicate:VI_QHS
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@ -3388,8 +3394,10 @@
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(match_operand 6 "const_int_operand")
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(match_operand 7 "const_int_operand")
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(match_operand 8 "const_int_operand")
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(match_operand 9 "const_int_operand")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(sat_int_plus_binop:VI_D
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(vec_duplicate:VI_D
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(match_operand:<VEL> 4 "reg_or_int_operand"))
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@ -3407,7 +3415,7 @@
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[] (rtx *operands, rtx boardcast_scalar) {
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emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
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operands[2], operands[3], boardcast_scalar, operands[5],
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operands[6], operands[7], operands[8]));
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operands[6], operands[7], operands[8], operands[9]));
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}))
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DONE;
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})
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@ -3421,8 +3429,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(sat_int_plus_binop:VI_D
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(vec_duplicate:VI_D
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(match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
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@ -3442,8 +3452,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(sat_int_plus_binop:VI_D
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(vec_duplicate:VI_D
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(sign_extend:<VEL>
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@ -3464,8 +3476,10 @@
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(match_operand 6 "const_int_operand")
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(match_operand 7 "const_int_operand")
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(match_operand 8 "const_int_operand")
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(match_operand 9 "const_int_operand")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(sat_int_minus_binop:VI_D
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(match_operand:VI_D 3 "register_operand")
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(vec_duplicate:VI_D
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@ -3483,7 +3497,7 @@
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[] (rtx *operands, rtx boardcast_scalar) {
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emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
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operands[2], operands[3], boardcast_scalar, operands[5],
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operands[6], operands[7], operands[8]));
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operands[6], operands[7], operands[8], operands[9]));
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}))
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DONE;
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})
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@ -3497,8 +3511,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(sat_int_minus_binop:VI_D
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(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
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(vec_duplicate:VI_D
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@ -3518,8 +3534,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(sat_int_minus_binop:VI_D
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(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
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(vec_duplicate:VI_D
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@ -3540,8 +3558,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(unspec:VI
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[(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
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(match_operand:VI 4 "register_operand" " vr, vr, vr, vr")] VSAT_OP)
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@ -3561,8 +3581,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(unspec:VI_QHS
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[(match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
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(match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
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@ -3581,8 +3603,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(unspec:VI
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[(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
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(match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSAT_SHIFT_OP)
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@ -3603,8 +3627,10 @@
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(match_operand 6 "const_int_operand")
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(match_operand 7 "const_int_operand")
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(match_operand 8 "const_int_operand")
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(match_operand 9 "const_int_operand")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(unspec:VI_D
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[(match_operand:VI_D 3 "register_operand")
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(match_operand:<VEL> 4 "reg_or_int_operand")] VSAT_ARITH_OP)
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@ -3621,7 +3647,7 @@
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[] (rtx *operands, rtx boardcast_scalar) {
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emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1],
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operands[2], operands[3], boardcast_scalar, operands[5],
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operands[6], operands[7], operands[8]));
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operands[6], operands[7], operands[8], operands[9]));
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}))
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DONE;
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})
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@ -3635,8 +3661,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(unspec:VI_D
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[(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
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(match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
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@ -3655,8 +3683,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(reg:SI VTYPE_REGNUM)
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(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
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(unspec:VI_D
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[(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
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(sign_extend:<VEL>
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@ -3677,8 +3707,10 @@
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(match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
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(match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
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(match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
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(match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
|
||||
(reg:SI VTYPE_REGNUM)
|
||||
(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
|
||||
(unspec:<V_DOUBLE_TRUNC>
|
||||
[(match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
|
||||
(match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")] VNCLIP)
|
||||
|
|
@ -3697,8 +3729,10 @@
|
|||
(match_operand 6 "const_int_operand" " i, i, i, i, i, i")
|
||||
(match_operand 7 "const_int_operand" " i, i, i, i, i, i")
|
||||
(match_operand 8 "const_int_operand" " i, i, i, i, i, i")
|
||||
(match_operand 9 "const_int_operand" " i, i, i, i, i, i")
|
||||
(reg:SI VL_REGNUM)
|
||||
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
|
||||
(reg:SI VTYPE_REGNUM)
|
||||
(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
|
||||
(unspec:<V_DOUBLE_TRUNC>
|
||||
[(match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
|
||||
(match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")] VNCLIP)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue