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RISC-V: allow vx instruction use "zero" as scalar register.

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li a5,0
  vdiv.vx v0,v1,a5 =======> vdiv.vx v0,v1,zero

gcc/ChangeLog:

	* config/riscv/vector.md: use "zero" reg.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/binop_vx_constraint-121.c: New test.
This commit is contained in:
Ju-Zhe Zhong 2023-02-07 15:49:16 +08:00 • committed by Kito Cheng
parent 316c83b158
commit 5e620b36cd
2 changed files with 88 additions and 24 deletions
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57
gcc/config/riscv/vector.md
View file

@ -1247,11 +1247,11 @@
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_commutative_binop:VI_QHS
(vec_duplicate:VI_QHS
(match_operand:<VEL> 4 "register_operand" " r, r"))
(match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_QHS 3 "register_operand" " vr, vr"))
(match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%4%p1"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
@ -1269,10 +1269,10 @@
(any_non_commutative_binop:VI_QHS
(match_operand:VI_QHS 3 "register_operand" " vr, vr")
(vec_duplicate:VI_QHS
(match_operand:<VEL> 4 "register_operand" " r, r")))
(match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ")))
(match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%4%p1"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
@ -1324,8 +1324,11 @@
rtx v = gen_reg_rtx (<MODE>mode);
if (riscv_vector::simm32_p (operands[4]))
operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[4]));
{
if (!rtx_equal_p (operands[4], const0_rtx))
operands[4] = force_reg (Pmode, operands[4]);
operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode, operands[4]);
}
else
{
if (CONST_INT_P (operands[4]))
@ -1356,11 +1359,11 @@
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_commutative_binop:VI_D
(vec_duplicate:VI_D
(match_operand:<VEL> 4 "register_operand" " r, r"))
(match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_D 3 "register_operand" " vr, vr"))
(match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%4%p1"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
@ -1378,11 +1381,11 @@
(any_commutative_binop:VI_D
(vec_duplicate:VI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 4 "register_operand" " r, r")))
(match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ")))
(match_operand:VI_D 3 "register_operand" " vr, vr"))
(match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%4%p1"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
@ -1411,8 +1414,11 @@
rtx v = gen_reg_rtx (<MODE>mode);
if (riscv_vector::simm32_p (operands[4]))
operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[4]));
{
if (!rtx_equal_p (operands[4], const0_rtx))
operands[4] = force_reg (Pmode, operands[4]);
operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode, operands[4]);
}
else
{
if (CONST_INT_P (operands[4]))
@ -1444,10 +1450,10 @@
(any_non_commutative_binop:VI_D
(match_operand:VI_D 3 "register_operand" " vr, vr")
(vec_duplicate:VI_D
(match_operand:<VEL> 4 "register_operand" " r, r")))
(match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ")))
(match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%4%p1"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
@ -1466,10 +1472,10 @@
(match_operand:VI_D 3 "register_operand" " vr, vr")
(vec_duplicate:VI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 4 "register_operand" " r, r"))))
(match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
(match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%4%p1"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
@ -1836,11 +1842,11 @@
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:VI_QHS
[(vec_duplicate:VI_QHS
(match_operand:<VEL> 4 "register_operand" " r, r"))
(match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_QHS 3 "register_operand" " vr, vr")] VMULH)
(match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
"TARGET_VECTOR"
"vmulh<v_su>.vx\t%0,%3,%4%p1"
"vmulh<v_su>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "vimul")
(set_attr "mode" "<MODE>")])
@ -1867,8 +1873,11 @@
rtx v = gen_reg_rtx (<MODE>mode);
if (riscv_vector::simm32_p (operands[4]))
operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[4]));
{
if (!rtx_equal_p (operands[4], const0_rtx))
operands[4] = force_reg (Pmode, operands[4]);
operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode, operands[4]);
}
else
{
if (CONST_INT_P (operands[4]))
@ -1899,11 +1908,11 @@
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:VFULLI_D
[(vec_duplicate:VFULLI_D
(match_operand:<VEL> 4 "register_operand" " r, r"))
(match_operand:<VEL> 4 "register_operand" " rJ, rJ"))
(match_operand:VFULLI_D 3 "register_operand" " vr, vr")] VMULH)
(match_operand:VFULLI_D 2 "vector_merge_operand" "0vu,0vu")))]
"TARGET_VECTOR"
"vmulh<v_su>.vx\t%0,%3,%4%p1"
"vmulh<v_su>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "vimul")
(set_attr "mode" "<MODE>")])
@ -1921,11 +1930,11 @@
(unspec:VFULLI_D
[(vec_duplicate:VFULLI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 4 "register_operand" " r, r")))
(match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ")))
(match_operand:VFULLI_D 3 "register_operand" " vr, vr")] VMULH)
(match_operand:VFULLI_D 2 "vector_merge_operand" "0vu,0vu")))]
"TARGET_VECTOR"
"vmulh<v_su>.vx\t%0,%3,%4%p1"
"vmulh<v_su>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "vimul")
(set_attr "mode" "<MODE>")])

55
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c Normal file
View file

@ -0,0 +1,55 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include "riscv_vector.h"
void f1 (void * in, void *out, int32_t x)
{
vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
vint32m1_t v3 = __riscv_vmulh_vx_i32m1 (v2, 0, 4);
__riscv_vse32_v_i32m1 (out, v3, 4);
}
void f2 (void * in, void *out, int32_t x)
{
vint64m1_t v = __riscv_vle64_v_i64m1 (in, 4);
vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in, 4);
vint64m1_t v3 = __riscv_vmulh_vx_i64m1 (v2, 0, 4);
__riscv_vse64_v_i64m1 (out, v3, 4);
}
void f3 (void * in, void *out, int32_t x)
{
vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, 0, 4);
__riscv_vse32_v_i32m1 (out, v3, 4);
}
void f4 (void * in, void *out, int32_t x)
{
vint64m1_t v = __riscv_vle64_v_i64m1 (in, 4);
vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in, 4);
vint64m1_t v3 = __riscv_vdiv_vx_i64m1 (v2, 0, 4);
__riscv_vse64_v_i64m1 (out, v3, 4);
}
void f5 (void * in, void *out, int32_t x)
{
vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
vint32m1_t v3 = __riscv_vrem_vx_i32m1 (v2, 0, 4);
__riscv_vse32_v_i32m1 (out, v3, 4);
}
void f6 (void * in, void *out, int32_t x)
{
vint64m1_t v = __riscv_vle64_v_i64m1 (in, 4);
vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in, 4);
vint64m1_t v3 = __riscv_vrem_vx_i64m1 (v2, 0, 4);
__riscv_vse64_v_i64m1 (out, v3, 4);
}
/* { dg-final { scan-assembler-times {vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,zero} 2 } } */
/* { dg-final { scan-assembler-times {vdiv\.vx\s+v[0-9]+,\s*v[0-9]+,zero} 2 } } */
/* { dg-final { scan-assembler-times {vrem\.vx\s+v[0-9]+,\s*v[0-9]+,zero} 2 } } */