[Patch AArch64_be] Fix some vec_concat big-endian confusions
* config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): New. (move_lo_quad_internal_be_<mode>): Likewise. (move_lo_quad_<mode>): Convert to define_expand. (aarch64_simd_move_hi_quad_<mode>): Gate on BYTES_BIG_ENDIAN. (aarch64_simd_move_hi_quad_be_<mode>): New. (move_hi_quad_<mode>): Use appropriate insn for BYTES_BIG_ENDIAN. (aarch64_combinez<mode>): Gate on BYTES_BIG_ENDIAN. (aarch64_combinez_be<mode>): New. (aarch64_combine<mode>): Convert to define_expand. (aarch64_combine_internal<mode>): New. (aarch64_simd_combine<mode>): Remove bogus RTL description. From-SVN: r212298
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
34386e79b3
commit
5a908485ae
2 changed files with 122 additions and 16 deletions
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@ -1,3 +1,17 @@
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2014-07-04 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): New.
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(move_lo_quad_internal_be_<mode>): Likewise.
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(move_lo_quad_<mode>): Convert to define_expand.
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(aarch64_simd_move_hi_quad_<mode>): Gate on BYTES_BIG_ENDIAN.
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(aarch64_simd_move_hi_quad_be_<mode>): New.
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(move_hi_quad_<mode>): Use appropriate insn for BYTES_BIG_ENDIAN.
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(aarch64_combinez<mode>): Gate on BYTES_BIG_ENDIAN.
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(aarch64_combinez_be<mode>): New.
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(aarch64_combine<mode>): Convert to define_expand.
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(aarch64_combine_internal<mode>): New.
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(aarch64_simd_combine<mode>): Remove bogus RTL description.
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2014-07-04 Tom de Vries <tom@codesourcery.com>
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* doc/md.texi (@subsection Constraint Modifier Characters): Clarify
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@ -942,14 +942,22 @@
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[(set_attr "type" "neon_minmax<q>")]
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)
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;; Move into low-half clearing high half to 0.
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;; vec_concat gives a new vector with the low elements from operand 1, and
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;; the high elements from operand 2. That is to say, given op1 = { a, b }
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;; op2 = { c, d }, vec_concat (op1, op2) = { a, b, c, d }.
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;; What that means, is that the RTL descriptions of the below patterns
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;; need to change depending on endianness.
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(define_insn "move_lo_quad_<mode>"
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;; Move to the low architectural bits of the register.
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;; On little-endian this is { operand, zeroes }
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;; On big-endian this is { zeroes, operand }
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(define_insn "move_lo_quad_internal_<mode>"
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[(set (match_operand:VQ 0 "register_operand" "=w,w,w")
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(vec_concat:VQ
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(match_operand:<VHALF> 1 "register_operand" "w,r,r")
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(vec_duplicate:<VHALF> (const_int 0))))]
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"TARGET_SIMD"
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"TARGET_SIMD && !BYTES_BIG_ENDIAN"
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"@
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dup\\t%d0, %1.d[0]
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fmov\\t%d0, %1
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@ -960,7 +968,39 @@
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(set_attr "length" "4")]
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)
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;; Move into high-half.
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(define_insn "move_lo_quad_internal_be_<mode>"
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[(set (match_operand:VQ 0 "register_operand" "=w,w,w")
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(vec_concat:VQ
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(vec_duplicate:<VHALF> (const_int 0))
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(match_operand:<VHALF> 1 "register_operand" "w,r,r")))]
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"TARGET_SIMD && BYTES_BIG_ENDIAN"
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"@
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dup\\t%d0, %1.d[0]
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fmov\\t%d0, %1
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dup\\t%d0, %1"
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[(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
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(set_attr "simd" "yes,*,yes")
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(set_attr "fp" "*,yes,*")
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(set_attr "length" "4")]
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)
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(define_expand "move_lo_quad_<mode>"
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[(match_operand:VQ 0 "register_operand")
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(match_operand:VQ 1 "register_operand")]
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"TARGET_SIMD"
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{
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_move_lo_quad_internal_be_<mode> (operands[0], operands[1]));
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else
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emit_insn (gen_move_lo_quad_internal_<mode> (operands[0], operands[1]));
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DONE;
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}
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)
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;; Move operand1 to the high architectural bits of the register, keeping
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;; the low architectural bits of operand2.
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;; For little-endian this is { operand2, operand1 }
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;; For big-endian this is { operand1, operand2 }
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(define_insn "aarch64_simd_move_hi_quad_<mode>"
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[(set (match_operand:VQ 0 "register_operand" "+w,w")
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@ -969,12 +1009,25 @@
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(match_dup 0)
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(match_operand:VQ 2 "vect_par_cnst_lo_half" ""))
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(match_operand:<VHALF> 1 "register_operand" "w,r")))]
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"TARGET_SIMD"
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"TARGET_SIMD && !BYTES_BIG_ENDIAN"
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"@
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ins\\t%0.d[1], %1.d[0]
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ins\\t%0.d[1], %1"
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[(set_attr "type" "neon_ins")
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(set_attr "length" "4")]
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[(set_attr "type" "neon_ins")]
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)
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(define_insn "aarch64_simd_move_hi_quad_be_<mode>"
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[(set (match_operand:VQ 0 "register_operand" "+w,w")
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(vec_concat:VQ
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(match_operand:<VHALF> 1 "register_operand" "w,r")
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(vec_select:<VHALF>
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(match_dup 0)
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(match_operand:VQ 2 "vect_par_cnst_hi_half" ""))))]
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"TARGET_SIMD && BYTES_BIG_ENDIAN"
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"@
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ins\\t%0.d[1], %1.d[0]
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ins\\t%0.d[1], %1"
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[(set_attr "type" "neon_ins")]
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)
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(define_expand "move_hi_quad_<mode>"
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@ -982,9 +1035,13 @@
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(match_operand:<VHALF> 1 "register_operand" "")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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emit_insn (gen_aarch64_simd_move_hi_quad_<mode> (operands[0],
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operands[1], p));
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, BYTES_BIG_ENDIAN);
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_aarch64_simd_move_hi_quad_be_<mode> (operands[0],
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operands[1], p));
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else
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emit_insn (gen_aarch64_simd_move_hi_quad_<mode> (operands[0],
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operands[1], p));
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DONE;
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})
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@ -2338,12 +2395,44 @@
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(vec_concat:<VDBL>
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(match_operand:VDIC 1 "register_operand" "w")
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(match_operand:VDIC 2 "aarch64_simd_imm_zero" "Dz")))]
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"TARGET_SIMD"
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"TARGET_SIMD && !BYTES_BIG_ENDIAN"
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"mov\\t%0.8b, %1.8b"
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[(set_attr "type" "neon_move<q>")]
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)
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(define_insn_and_split "aarch64_combine<mode>"
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(define_insn "*aarch64_combinez_be<mode>"
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[(set (match_operand:<VDBL> 0 "register_operand" "=&w")
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(vec_concat:<VDBL>
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(match_operand:VDIC 2 "aarch64_simd_imm_zero" "Dz")
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(match_operand:VDIC 1 "register_operand" "w")))]
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"TARGET_SIMD && BYTES_BIG_ENDIAN"
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"mov\\t%0.8b, %1.8b"
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[(set_attr "type" "neon_move<q>")]
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)
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(define_expand "aarch64_combine<mode>"
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[(match_operand:<VDBL> 0 "register_operand")
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(match_operand:VDC 1 "register_operand")
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(match_operand:VDC 2 "register_operand")]
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"TARGET_SIMD"
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{
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rtx op1, op2;
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if (BYTES_BIG_ENDIAN)
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{
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op1 = operands[2];
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op2 = operands[1];
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}
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else
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{
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op1 = operands[1];
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op2 = operands[2];
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}
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emit_insn (gen_aarch64_combine_internal<mode> (operands[0], op1, op2));
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DONE;
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}
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)
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(define_insn_and_split "aarch64_combine_internal<mode>"
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[(set (match_operand:<VDBL> 0 "register_operand" "=&w")
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(vec_concat:<VDBL> (match_operand:VDC 1 "register_operand" "w")
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(match_operand:VDC 2 "register_operand" "w")))]
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@ -2352,16 +2441,19 @@
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
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if (BYTES_BIG_ENDIAN)
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aarch64_split_simd_combine (operands[0], operands[2], operands[1]);
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else
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aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
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DONE;
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}
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[(set_attr "type" "multiple")]
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)
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(define_expand "aarch64_simd_combine<mode>"
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[(set (match_operand:<VDBL> 0 "register_operand" "=&w")
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(vec_concat:<VDBL> (match_operand:VDC 1 "register_operand" "w")
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(match_operand:VDC 2 "register_operand" "w")))]
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[(match_operand:<VDBL> 0 "register_operand")
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(match_operand:VDC 1 "register_operand")
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(match_operand:VDC 2 "register_operand")]
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"TARGET_SIMD"
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{
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emit_insn (gen_move_lo_quad_<Vdbl> (operands[0], operands[1]));
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