re PR target/13380 (An unrecognized insn.)
PR target/13380. * config/m32r/m32r.md: Replace (reg:SI 17) with (reg:CC 17) or (ne:SI (reg:CC 17) (const_int 0)). Be specific about modes wherever possible. From-SVN: r75586
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
81ad38a60d
commit
58ebda9c2a
2 changed files with 103 additions and 96 deletions
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@ -1,3 +1,10 @@
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2004-01-09 Kazu Hirata <kazu@cs.umass.edu>
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PR target/13380.
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* config/m32r/m32r.md: Replace (reg:SI 17) with (reg:CC 17)
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or (ne:SI (reg:CC 17) (const_int 0)).
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Be specific about modes wherever possible.
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2004-01-09 Kazu Hirata <kazu@cs.umass.edu>
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* config/m32r/m32r.c (m32r_expand_block_move): Call
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@ -579,7 +579,7 @@
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(define_insn "*load_sda_base"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec [(const_int 0)] 2))]
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(unspec:SI [(const_int 0)] 2))]
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""
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"ld24 %0,#_SDA_BASE_"
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[(set_attr "type" "int4")
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@ -900,7 +900,7 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (match_operand:DI 1 "register_operand" "%0")
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(match_operand:DI 2 "register_operand" "r")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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""
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"#"
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[(set_attr "type" "multi")
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@ -911,23 +911,23 @@
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[(set (match_operand:DI 0 "register_operand" "")
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(plus:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "register_operand" "")))
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(clobber (match_operand 3 "" ""))]
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(clobber (reg:CC 17))]
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"reload_completed"
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[(parallel [(set (match_dup 3)
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[(parallel [(set (reg:CC 17)
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(const_int 0))
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(use (match_dup 4))])
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(parallel [(set (match_dup 4)
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(plus:SI (match_dup 4)
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(plus:SI (match_dup 5)
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(match_dup 3))))
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(set (match_dup 3)
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(unspec [(const_int 0)] 3))])
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))])
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(parallel [(set (match_dup 6)
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(plus:SI (match_dup 6)
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(plus:SI (match_dup 7)
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(match_dup 3))))
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(set (match_dup 3)
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(unspec [(const_int 0)] 3))])]
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))])]
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"
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{
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operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
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@ -937,7 +937,7 @@
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}")
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(define_insn "*clear_c"
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[(set (reg:SI 17)
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[(set (reg:CC 17)
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(const_int 0))
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(use (match_operand:SI 0 "register_operand" "r"))]
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""
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@ -949,9 +949,9 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(plus:SI (match_operand:SI 1 "register_operand" "%0")
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(plus:SI (match_operand:SI 2 "register_operand" "r")
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(reg:SI 17))))
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(set (reg:SI 17)
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(unspec [(const_int 0)] 3))]
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))]
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""
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"addx %0,%2"
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[(set_attr "type" "int2")
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@ -970,7 +970,7 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:DI 2 "register_operand" "r")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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""
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"#"
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[(set_attr "type" "multi")
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@ -981,23 +981,23 @@
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[(set (match_operand:DI 0 "register_operand" "")
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(minus:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "register_operand" "")))
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(clobber (match_operand 3 "" ""))]
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(clobber (reg:CC 17))]
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"reload_completed"
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[(parallel [(set (match_dup 3)
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[(parallel [(set (reg:CC 17)
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(const_int 0))
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(use (match_dup 4))])
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(parallel [(set (match_dup 4)
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(minus:SI (match_dup 4)
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(minus:SI (match_dup 5)
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(match_dup 3))))
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(set (match_dup 3)
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(unspec [(const_int 0)] 3))])
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))])
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(parallel [(set (match_dup 6)
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(minus:SI (match_dup 6)
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(minus:SI (match_dup 7)
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(match_dup 3))))
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(set (match_dup 3)
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(unspec [(const_int 0)] 3))])]
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))])]
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"
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{
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operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
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@ -1010,9 +1010,9 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(minus:SI (match_operand:SI 1 "register_operand" "%0")
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(minus:SI (match_operand:SI 2 "register_operand" "r")
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(reg:SI 17))))
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(set (reg:SI 17)
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(unspec [(const_int 0)] 3))]
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))]
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""
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"subx %0,%2"
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[(set_attr "type" "int2")
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@ -1241,7 +1241,7 @@
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;; preferred.
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(define_expand "cmpsi"
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[(set (reg:SI 17)
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[(set (reg:CC 17)
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(compare:CC (match_operand:SI 0 "register_operand" "")
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(match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
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""
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@ -1253,8 +1253,8 @@
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}")
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(define_insn "cmp_eqsi_zero_insn"
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[(set (reg:SI 17)
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(eq:SI (match_operand:SI 0 "register_operand" "r,r")
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[(set (reg:CC 17)
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(eq:CC (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
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"TARGET_M32RX || TARGET_M32R2"
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"@
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@ -1268,8 +1268,8 @@
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;; is quite inefficient. However, it is rarely used.
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(define_insn "cmp_eqsi_insn"
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[(set (reg:SI 17)
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(eq:SI (match_operand:SI 0 "register_operand" "r,r")
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[(set (reg:CC 17)
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(eq:CC (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
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(clobber (match_scratch:SI 2 "=&r,&r"))]
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""
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@ -1293,8 +1293,8 @@
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(set_attr "length" "8,8")])
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(define_insn "cmp_ltsi_insn"
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[(set (reg:SI 17)
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(lt:SI (match_operand:SI 0 "register_operand" "r,r")
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[(set (reg:CC 17)
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(lt:CC (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
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""
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"@
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@ -1304,8 +1304,8 @@
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(set_attr "length" "2,4")])
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(define_insn "cmp_ltusi_insn"
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[(set (reg:SI 17)
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(ltu:SI (match_operand:SI 0 "register_operand" "r,r")
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[(set (reg:CC 17)
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(ltu:CC (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
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""
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"@
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@ -1696,7 +1696,7 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(eq:SI (match_operand:SI 1 "register_operand" "%r")
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(match_operand:SI 2 "reg_or_zero_operand" "rP")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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"TARGET_M32RX || TARGET_M32R2"
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"#"
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[(set_attr "type" "multi")
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@ -1706,20 +1706,20 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(eq:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "reg_or_zero_operand" "")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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"TARGET_M32RX || TARGET_M32R2"
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[(set (reg:SI 17)
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(eq:SI (match_dup 1)
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[(set (reg:CC 17)
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(eq:CC (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(reg:SI 17))]
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(ne:SI (reg:CC 17) (const_int 0)))]
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"")
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(define_insn "seq_zero_insn"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(eq:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 0)))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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"TARGET_M32R"
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"#"
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[(set_attr "type" "multi")
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@ -1729,7 +1729,7 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(eq:SI (match_operand:SI 1 "register_operand" "")
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(const_int 0)))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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"TARGET_M32R"
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[(match_dup 3)]
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"
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@ -1748,7 +1748,7 @@
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[(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
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(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
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(clobber (reg:SI 17))
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(clobber (reg:CC 17))
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(clobber (match_scratch:SI 3 "=1,2,&r,r"))]
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"TARGET_M32R"
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"#"
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@ -1759,7 +1759,7 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(eq:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "reg_or_eq_int16_operand" "")))
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(clobber (reg:SI 17))
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(clobber (reg:CC 17))
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(clobber (match_scratch:SI 3 ""))]
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"TARGET_M32R && reload_completed"
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[(match_dup 4)]
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@ -1837,7 +1837,7 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ne:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 0)))
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(clobber (reg:SI 17))
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(clobber (reg:CC 17))
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(clobber (match_scratch:SI 2 "=&r"))]
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""
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"#"
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@ -1848,16 +1848,16 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(ne:SI (match_operand:SI 1 "register_operand" "")
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(const_int 0)))
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(clobber (reg:SI 17))
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(clobber (reg:CC 17))
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(clobber (match_scratch:SI 2 ""))]
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"reload_completed"
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[(set (match_dup 2)
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(const_int 0))
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(set (reg:SI 17)
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(ltu:SI (match_dup 2)
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(set (reg:CC 17)
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(ltu:CC (match_dup 2)
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(match_dup 1)))
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(set (match_dup 0)
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(reg:SI 17))]
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(ne:SI (reg:CC 17) (const_int 0)))]
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"")
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(define_expand "slt"
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@ -1887,7 +1887,7 @@
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(lt:SI (match_operand:SI 1 "register_operand" "r,r")
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(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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""
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"#"
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[(set_attr "type" "multi")
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@ -1897,13 +1897,13 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(lt:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "reg_or_int16_operand" "")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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""
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[(set (reg:SI 17)
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(lt:SI (match_dup 1)
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[(set (reg:CC 17)
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(lt:CC (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(reg:SI 17))]
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(ne:SI (reg:CC 17) (const_int 0)))]
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"")
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(define_expand "sle"
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@ -1950,7 +1950,7 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(le:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "register_operand" "r")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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""
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"#"
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[(set_attr "type" "multi")
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@ -1960,13 +1960,13 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(le:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "register_operand" "")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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"!optimize_size"
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[(set (reg:SI 17)
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(lt:SI (match_dup 2)
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[(set (reg:CC 17)
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(lt:CC (match_dup 2)
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(match_dup 1)))
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(set (match_dup 0)
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(reg:SI 17))
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(ne:SI (reg:CC 17) (const_int 0)))
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(set (match_dup 0)
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(xor:SI (match_dup 0)
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(const_int 1)))]
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@ -1978,13 +1978,13 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(le:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "register_operand" "")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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"optimize_size"
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[(set (reg:SI 17)
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(lt:SI (match_dup 2)
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[(set (reg:CC 17)
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(lt:CC (match_dup 2)
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(match_dup 1)))
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(set (match_dup 0)
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(reg:SI 17))
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(ne:SI (reg:CC 17) (const_int 0)))
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(set (match_dup 0)
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(plus:SI (match_dup 0)
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(const_int -1)))
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@ -2042,7 +2042,7 @@
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(ge:SI (match_operand:SI 1 "register_operand" "r,r")
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(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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""
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"#"
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[(set_attr "type" "multi")
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@ -2052,13 +2052,13 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(ge:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "reg_or_int16_operand" "")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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"!optimize_size"
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[(set (reg:SI 17)
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(lt:SI (match_dup 1)
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[(set (reg:CC 17)
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(lt:CC (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(reg:SI 17))
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(ne:SI (reg:CC 17) (const_int 0)))
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(set (match_dup 0)
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(xor:SI (match_dup 0)
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(const_int 1)))]
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@ -2070,13 +2070,13 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(ge:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "reg_or_int16_operand" "")))
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(clobber (reg:SI 17))]
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(clobber (reg:CC 17))]
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||||
"optimize_size"
|
||||
[(set (reg:SI 17)
|
||||
(lt:SI (match_dup 1)
|
||||
[(set (reg:CC 17)
|
||||
(lt:CC (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(reg:SI 17))
|
||||
(ne:SI (reg:CC 17) (const_int 0)))
|
||||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0)
|
||||
(const_int -1)))
|
||||
|
|
@ -2111,7 +2111,7 @@
|
|||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(ltu:SI (match_operand:SI 1 "register_operand" "r,r")
|
||||
(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
|
||||
(clobber (reg:SI 17))]
|
||||
(clobber (reg:CC 17))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "type" "multi")
|
||||
|
|
@ -2121,13 +2121,13 @@
|
|||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(ltu:SI (match_operand:SI 1 "register_operand" "")
|
||||
(match_operand:SI 2 "reg_or_int16_operand" "")))
|
||||
(clobber (reg:SI 17))]
|
||||
(clobber (reg:CC 17))]
|
||||
""
|
||||
[(set (reg:SI 17)
|
||||
(ltu:SI (match_dup 1)
|
||||
[(set (reg:CC 17)
|
||||
(ltu:CC (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(reg:SI 17))]
|
||||
(ne:SI (reg:CC 17) (const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_expand "sleu"
|
||||
|
|
@ -2171,7 +2171,7 @@
|
|||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(leu:SI (match_operand:SI 1 "register_operand" "r")
|
||||
(match_operand:SI 2 "register_operand" "r")))
|
||||
(clobber (reg:SI 17))]
|
||||
(clobber (reg:CC 17))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "type" "multi")
|
||||
|
|
@ -2181,13 +2181,13 @@
|
|||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(leu:SI (match_operand:SI 1 "register_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")))
|
||||
(clobber (reg:SI 17))]
|
||||
(clobber (reg:CC 17))]
|
||||
"!optimize_size"
|
||||
[(set (reg:SI 17)
|
||||
(ltu:SI (match_dup 2)
|
||||
[(set (reg:CC 17)
|
||||
(ltu:CC (match_dup 2)
|
||||
(match_dup 1)))
|
||||
(set (match_dup 0)
|
||||
(reg:SI 17))
|
||||
(ne:SI (reg:CC 17) (const_int 0)))
|
||||
(set (match_dup 0)
|
||||
(xor:SI (match_dup 0)
|
||||
(const_int 1)))]
|
||||
|
|
@ -2199,13 +2199,13 @@
|
|||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(leu:SI (match_operand:SI 1 "register_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")))
|
||||
(clobber (reg:SI 17))]
|
||||
(clobber (reg:CC 17))]
|
||||
"optimize_size"
|
||||
[(set (reg:SI 17)
|
||||
(ltu:SI (match_dup 2)
|
||||
[(set (reg:CC 17)
|
||||
(ltu:CC (match_dup 2)
|
||||
(match_dup 1)))
|
||||
(set (match_dup 0)
|
||||
(reg:SI 17))
|
||||
(ne:SI (reg:CC 17) (const_int 0)))
|
||||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0)
|
||||
(const_int -1)))
|
||||
|
|
@ -2263,7 +2263,7 @@
|
|||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(geu:SI (match_operand:SI 1 "register_operand" "r,r")
|
||||
(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
|
||||
(clobber (reg:SI 17))]
|
||||
(clobber (reg:CC 17))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "type" "multi")
|
||||
|
|
@ -2273,13 +2273,13 @@
|
|||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(geu:SI (match_operand:SI 1 "register_operand" "")
|
||||
(match_operand:SI 2 "reg_or_int16_operand" "")))
|
||||
(clobber (reg:SI 17))]
|
||||
(clobber (reg:CC 17))]
|
||||
"!optimize_size"
|
||||
[(set (reg:SI 17)
|
||||
(ltu:SI (match_dup 1)
|
||||
[(set (reg:CC 17)
|
||||
(ltu:CC (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(reg:SI 17))
|
||||
(ne:SI (reg:CC 17) (const_int 0)))
|
||||
(set (match_dup 0)
|
||||
(xor:SI (match_dup 0)
|
||||
(const_int 1)))]
|
||||
|
|
@ -2291,13 +2291,13 @@
|
|||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(geu:SI (match_operand:SI 1 "register_operand" "")
|
||||
(match_operand:SI 2 "reg_or_int16_operand" "")))
|
||||
(clobber (reg:SI 17))]
|
||||
(clobber (reg:CC 17))]
|
||||
"optimize_size"
|
||||
[(set (reg:SI 17)
|
||||
(ltu:SI (match_dup 1)
|
||||
[(set (reg:CC 17)
|
||||
(ltu:CC (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(reg:SI 17))
|
||||
(ne:SI (reg:CC 17) (const_int 0)))
|
||||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0)
|
||||
(const_int -1)))
|
||||
|
|
@ -2307,7 +2307,7 @@
|
|||
|
||||
(define_insn "movcc_insn"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(reg:SI 17))]
|
||||
(ne:SI (reg:CC 17) (const_int 0)))]
|
||||
""
|
||||
"mvfc %0, cbr"
|
||||
[(set_attr "type" "misc")
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue