Move C++ SVE tests to g++.target/aarch64/sve

2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
	* g++.dg/other/sve_const_pred_1.C: Rename to...
	* g++.target/aarch64/sve/const_pred_1.C: ...this.  Remove aarch64
	target selectors and explicit -march options.
	* g++.dg/other/sve_const_pred_2.C: Rename to...
	* g++.target/aarch64/sve/const_pred_2.C: ...this and adjust likewise.
	* g++.dg/other/sve_const_pred_3.C: Rename to...
	* g++.target/aarch64/sve/const_pred_3.C: ...this and adjust likewise.
	* g++.dg/other/sve_const_pred_4.C: Rename to...
	* g++.target/aarch64/sve/const_pred_4.C: ...this and adjust likewise.
	* g++.dg/other/sve_tls_2.C: Rename to...
	* g++.target/aarch64/sve/tls_2.C: ...this and adjust likewise.
	* g++.dg/other/sve_vcond_1.C: Rename to...
	* g++.target/aarch64/sve/vcond_1.C: ...this and adjust likewise.
	* g++.dg/other/sve_vcond_1_run.C: Rename to...
	* g++.target/aarch64/sve/vcond_1_run.C: ...this and adjust likewise.

From-SVN: r260038

gcc/testsuite/ChangeLog

@@ -1,3 +1,21 @@
+2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* g++.dg/other/sve_const_pred_1.C: Rename to...
+	* g++.target/aarch64/sve/const_pred_1.C: ...this.  Remove aarch64
+	target selectors and explicit -march options.
+	* g++.dg/other/sve_const_pred_2.C: Rename to...
+	* g++.target/aarch64/sve/const_pred_2.C: ...this and adjust likewise.
+	* g++.dg/other/sve_const_pred_3.C: Rename to...
+	* g++.target/aarch64/sve/const_pred_3.C: ...this and adjust likewise.
+	* g++.dg/other/sve_const_pred_4.C: Rename to...
+	* g++.target/aarch64/sve/const_pred_4.C: ...this and adjust likewise.
+	* g++.dg/other/sve_tls_2.C: Rename to...
+	* g++.target/aarch64/sve/tls_2.C: ...this and adjust likewise.
+	* g++.dg/other/sve_vcond_1.C: Rename to...
+	* g++.target/aarch64/sve/vcond_1.C: ...this and adjust likewise.
+	* g++.dg/other/sve_vcond_1_run.C: Rename to...
+	* g++.target/aarch64/sve/vcond_1_run.C: ...this and adjust likewise.
+
 2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>
 
 	PR testsuite/85586

gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C

@@ -1,5 +1,5 @@
-/* { dg-do compile { target aarch64*-*-* } } */
-/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msve-vector-bits=256" } */
 
 #include <stdint.h>
 

gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C

@@ -1,5 +1,5 @@
-/* { dg-do compile { target aarch64*-*-* } } */
-/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msve-vector-bits=256" } */
 
 #include <stdint.h>
 

gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C

@@ -1,5 +1,5 @@
-/* { dg-do compile { target aarch64*-*-* } } */
-/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msve-vector-bits=256" } */
 
 #include <stdint.h>
 

gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C

@@ -1,5 +1,5 @@
-/* { dg-do compile { target aarch64*-*-* } } */
-/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msve-vector-bits=256" } */
 
 #include <stdint.h>
 

gcc/testsuite/g++.target/aarch64/sve/tls_2.C

@@ -1,6 +1,6 @@
-/* { dg-do compile { target aarch64*-*-* } } */
+/* { dg-do compile } */
 /* { dg-require-effective-target tls } */
-/* { dg-options "-O2 -march=armv8.2-a+sve -fPIC -msve-vector-bits=256" } */
+/* { dg-options "-O2 -fPIC -msve-vector-bits=256" } */
 
 #include <stdint.h>
 

gcc/testsuite/g++.target/aarch64/sve/vcond_1.C

@@ -1,5 +1,5 @@
 /* { dg-do assemble { target { aarch64_asm_sve_ok && { ! ilp32 } } } } */
-/* { dg-options "-march=armv8.2-a+sve -O -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 typedef __INT8_TYPE__ vnx16qi __attribute__((vector_size(32)));
 typedef __INT16_TYPE__ vnx8hi __attribute__((vector_size(32)));

gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C

@@ -1,6 +1,6 @@
 /* { dg-do run { target aarch64_sve_hw } } */
-/* { dg-options "-O -march=armv8.2-a+sve" } */
-/* { dg-options "-O -march=armv8.2-a+sve -msve-vector-bits=256" { target aarch64_sve256_hw } } */
+/* { dg-options "-O" } */
+/* { dg-options "-O -msve-vector-bits=256" { target aarch64_sve256_hw } } */
 
 #include "sve_vcond_1.c"