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RISC-V: xtheadmemidx: Document inline asm issue with memory constraint

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The XTheadMemIdx support relies on the fact that memory operands that
can be expressed by XTheadMemIdx instructions, will only appear as
operands of such instructions.  For internal instruction generation
this is guaranteed by the implemenation.  However, in case of inline
assembly, this guarantee is not given and we cannot differentiate
these two cases when printing the operand:

  asm volatile ("sd	%1,%0" : "=m"(*tmp) : "r"(val));
  asm volatile ("th.srd %1,%0" : "=m"(*tmp) : "r"(val));

If XTheadMemIdx is enabled, then the address will be printed as if an
XTheadMemIdx instruction is emitted, which is obviously wrong in the
first case.

There might be solutions to handle this (e.g. using TARGET_MEM_CONSTRAINT
or extending the mnemonics to accept the standard operands for
XTheadMemIdx instructions), but let's document this behavior for now
as a known issue by adding xfail tests until we have an acceptable fix.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadmemidx-inline-asm-1.c: New test.

Reported-by: Jin Ma <jinma@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner 2023-12-05 02:54:52 +01:00
parent 8c09c73adf
commit 570d74119d
1 changed files with 26 additions and 0 deletions
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26
gcc/testsuite/gcc.target/riscv/xtheadmemidx-inline-asm-1.c Normal file
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/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
/* { dg-options "-march=rv64gc_xtheadmemidx -mabi=lp64" } */
/* XTheadMemIdx support is implemented such that reg+reg addressing mode
loads/stores are preferred over standard loads/stores.
If this order changed using inline assembly, the result will be invalid
instructions. This test serves the purpose of documenting this
limitation until a solution is available. */
void foo (void *p, unsigned long off, unsigned long val)
{
unsigned long *tmp = (unsigned long*)(p + off);
asm volatile ("sd %1,%0" : "=m"(*tmp) : "r"(val));
}
void bar (void *p, unsigned long off, unsigned long val)
{
unsigned long *tmp = (unsigned long*)(p + off);
asm volatile ("th.srd %1,%0" : "=m"(*tmp) : "r"(val));
}
/* { dg-final { scan-assembler "sd\t\[a-z\]\[0-9\]+,0\\(\[a-z\]\[0-9\]+\\)" { xfail *-*-* } } } */
/* { dg-final { scan-assembler-not "sd\t\[a-z\]\[0-9\]+,\[a-z\]\[0-9\]+,\[a-z\]\[0-9\]+,0" { xfail *-*-* } } } */
/* { dg-final { scan-assembler "th\.srd\t\[a-z\]\[0-9\]+,\[a-z\]\[0-9\]+,\[a-z\]\[0-9\]+,0" } } */
/* { dg-final { scan-assembler-not "th\.srd\t\[a-z\]\[0-9\]+,0\\(\[a-z\]\[0-9\]+\\)" } } */