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RISC-V: Update testcase due to message update

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gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-27.c: Update scan message.
	* gcc.target/riscv/arch-28.c: Ditto.
	* gcc.target/riscv/attribute-10.c: Ditto.
	* gcc.target/riscv/rvv/base/big_endian-2.c: Ditto.
	* gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Ditto.
	* gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Ditto.
This commit is contained in:
Kito Cheng 2024-01-19 17:52:44 +08:00
parent 19260a04ba
commit 54519030b0
6 changed files with 6 additions and 6 deletions
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2
gcc/testsuite/gcc.target/riscv/arch-27.c
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@ -4,4 +4,4 @@ int foo()
{
}
/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target *-*-* } 0 } */
/* { dg-error "i, e or g must be the first extension" "" { target *-*-* } 0 } */

2
gcc/testsuite/gcc.target/riscv/arch-28.c
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@ -4,4 +4,4 @@ int foo()
{
}
/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target *-*-* } 0 } */
/* { dg-error "i, e or g must be the first extension" "" { target *-*-* } 0 } */

2
gcc/testsuite/gcc.target/riscv/attribute-10.c
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@ -5,4 +5,4 @@ int foo()
}
/* { dg-error "extension 'u' is unsupported standard single letter extension" "" { target { "riscv*-*-*" } } 0 } */
/* { dg-error "extension 'n' is unsupported standard single letter extension" "" { target { "riscv*-*-*" } } 0 } */
/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target { "riscv*-*-*" } } 0 } */
/* { dg-error "i, e or g must be the first extension" "" { target { "riscv*-*-*" } } 0 } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c
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@ -2,4 +2,4 @@
/* { dg-options "-march=rv64gc_zve32x -mabi=lp64d -mbig-endian -O3" } */
#pragma riscv intrinsic "vector"
vint32m1_t foo (vint32m1_t) {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC cannot support RVV in big-endian mode" }
vint32m1_t foo (vint32m1_t) {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support RVV in big-endian mode" }

2
gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
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@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */
void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" }
void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }

2
gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile } */
/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */
void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" }
void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }