diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 886a7e26fbf..f1a3d98d139 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2000-05-27 Richard Henderson + + * config/d30v/d30v.c (d30v_print_operand): Handle ':'. + * config/d30v/d30v.h (PRINT_OPERAND_PUNCT_VALID_P): Accept ':'. + * config/d30v/d30v.md (attr predicable): New. + (all insn patterns): Mark non-predicable patterns; use %: on the rest. + (andsi3*): Unify into one pattern. + (iorsi3*, xorsi3*): Likewise. + (peephole2 patterns): Use peep2_reg_dead_p; verify not a + conditional return. + (old cond_exec patterns): Remove. + (define_cond_exec): New. + Sat May 27 11:01:27 2000 Richard Kenner * tree.h (TREE_CODE_LENGTH): New macro. diff --git a/gcc/config/d30v/d30v.c b/gcc/config/d30v/d30v.c index 7421bfc1343..749aa1b4d30 100644 --- a/gcc/config/d30v/d30v.c +++ b/gcc/config/d30v/d30v.c @@ -2949,6 +2949,13 @@ d30v_print_operand (stream, x, letter) d30v_print_operand (stream, split_values[ letter == 'L' ], '\0'); break; + case ':': /* Output the condition for the current insn. */ + x = current_insn_predicate; + if (x == NULL_RTX) + break; + letter = 'T'; + /* FALLTHRU */ + case 'F': /* Print an appropriate suffix for a false comparision. */ case 'T': /* Print an appropriate suffix for a true comparision. */ /* Note that the sense of appropriate suffix is for conditional execution diff --git a/gcc/config/d30v/d30v.h b/gcc/config/d30v/d30v.h index 6b7b97405ae..c97ff98032b 100644 --- a/gcc/config/d30v/d30v.h +++ b/gcc/config/d30v/d30v.h @@ -4953,7 +4953,7 @@ do { \ `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no punctuation characters (except for the standard one, `%') are used in this way. */ -#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '.') +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '.' || (CODE) == ':') /* A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory reference whose address is X. X diff --git a/gcc/config/d30v/d30v.md b/gcc/config/d30v/d30v.md index 0e1d1561fdc..14f6a46c493 100644 --- a/gcc/config/d30v/d30v.md +++ b/gcc/config/d30v/d30v.md @@ -351,24 +351,30 @@ ;; Length in word units (define_attr "length" "" (cond [(eq_attr "type" "iu,mu,either,scmp,sload,mul,scarry,") - (const_int 4) + (const_int 4) (eq_attr "type" "long,lcmp,lload,lcarry") - (const_int 8) - (eq_attr "type" "multi,unknown") (const_int 64) ;; set higher to give a fudge factor - (eq_attr "type" "br") (if_then_else (and (ge (minus (pc) (match_dup 0)) - (const_int -1048576)) - (lt (minus (pc) (match_dup 0)) - (const_int 1048575))) - (const_int 4) - (const_int 8)) - (eq_attr "type" "br2") (if_then_else (and (ge (minus (pc) (match_dup 0)) - (const_int -16384)) - (lt (minus (pc) (match_dup 0)) - (const_int 16383))) - (const_int 4) - (const_int 8))] + (const_int 8) + (eq_attr "type" "multi,unknown") + (const_int 64) ;; set higher to give a fudge factor + (eq_attr "type" "br") + (if_then_else (and (ge (minus (pc) (match_dup 0)) + (const_int -1048576)) + (lt (minus (pc) (match_dup 0)) + (const_int 1048575))) + (const_int 4) + (const_int 8)) + (eq_attr "type" "br2") + (if_then_else (and (ge (minus (pc) (match_dup 0)) + (const_int -16384)) + (lt (minus (pc) (match_dup 0)) + (const_int 16383))) + (const_int 4) + (const_int 8)) + ] (const_int 8))) +(define_attr "predicable" "no,yes" + (const_string "yes")) ;; :::::::::::::::::::: ;; :: @@ -679,16 +685,16 @@ (match_operand:QI 1 "move_input_operand" "dI,i,Q,m,d,d,O,O,c,d"))] "register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode)" "@ - or %0,%.,%1 - or %0,%.,%1 - ldb %0,%M1 - ldb %0,%M1 - stb %1,%M0 - stb %1,%M0 - stb %.,%M0 - stb %.,%M0 - mvfsys %0,%1 - mvtsys %0,%1" + or%: %0,%.,%1 + or%: %0,%.,%1 + ldb%: %0,%M1 + ldb%: %0,%M1 + stb%: %1,%M0 + stb%: %1,%M0 + stb%: %.,%M0 + stb%: %.,%M0 + mvfsys%: %0,%1 + mvtsys%: %0,%1" [(set_attr "length" "4,8,4,8,4,8,4,8,4,4") (set_attr "type" "either,long,sload,lload,mu,long,mu,long,mu,mu")]) @@ -709,16 +715,16 @@ (match_operand:HI 1 "move_input_operand" "dI,i,Q,m,d,d,O,O,c,d"))] "register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode)" "@ - or %0,%.,%1 - or %0,%.,%1 - ldh %0,%M1 - ldh %0,%M1 - sth %1,%M0 - sth %1,%M0 - sth %.,%M0 - sth %.,%M0 - mvfsys %0,%1 - mvtsys %0,%1" + or%: %0,%.,%1 + or%: %0,%.,%1 + ldh%: %0,%M1 + ldh%: %0,%M1 + sth%: %1,%M0 + sth%: %1,%M0 + sth%: %.,%M0 + sth%: %.,%M0 + mvfsys%: %0,%1 + mvtsys%: %0,%1" [(set_attr "length" "4,8,4,8,4,8,4,8,4,4") (set_attr "type" "either,long,sload,lload,mu,long,mu,long,mu,mu")]) @@ -755,17 +761,17 @@ (match_operand:SI 1 "move_input_operand" "dI,F,i,Q,m,d,d,O,O,c,d"))] "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)" "@ - or %0,%.,%1 - or %0,%.,%L1 - or %0,%.,%1 - ldw %0,%M1 - ldw %0,%M1 - stw %1,%M0 - stw %1,%M0 - stw %.,%M0 - stw %.,%M0 - mvfsys %0,%1 - mvtsys %0,%1" + or%: %0,%.,%1 + or%: %0,%.,%L1 + or%: %0,%.,%1 + ldw%: %0,%M1 + ldw%: %0,%M1 + stw%: %1,%M0 + stw%: %1,%M0 + stw%: %.,%M0 + stw%: %.,%M0 + mvfsys%: %0,%1 + mvtsys%: %0,%1" [(set_attr "length" "4,8,8,4,8,4,8,4,8,4,4") (set_attr "type" "either,long,long,sload,lload,mu,long,mu,long,mu,mu")]) @@ -818,15 +824,15 @@ (match_operand:SF 1 "move_input_operand" "d,G,F,Q,m,d,d,G,G"))] "register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode)" "@ - or %0,%.,%1 - or %0,%.,0 - or %0,%.,%f1 - ldw %0,%M1 - ldw %0,%M1 - stw %1,%M0 - stw %1,%M0 - stw %.,%M0 - stw %.,%M0" + or%: %0,%.,%1 + or%: %0,%.,0 + or%: %0,%.,%f1 + ldw%: %0,%M1 + ldw%: %0,%M1 + stw%: %1,%M0 + stw%: %1,%M0 + stw%: %.,%M0 + stw%: %.,%M0" [(set_attr "length" "4,4,8,4,8,4,8,4,8") (set_attr "type" "either,either,long,sload,lload,mu,long,mu,long")]) @@ -879,17 +885,17 @@ (match_operand:CC 1 "move_input_operand" "f,O,N,b,f,d,dON,*Q,*m,*d,*d"))] "!memory_operand (operands[0], CCmode) || !memory_operand (operands[1], CCmode)" "@ - orfg %0,%1,%1 - andfg %0,%0,0 - orfg %0,%0,1 + orfg%: %0,%1,%1 + andfg%: %0,%0,0 + orfg%: %0,%0,1 # - mvfsys %0,%1 - cmpne %0,%1,0 - or %0,%.,%1 - ldb %0,%M1 - ldb %0,%M1 - stb %1,%M0 - stb %1,%M0" + mvfsys%: %0,%1 + cmpne%: %0,%1,0 + or%: %0,%.,%1 + ldb%: %0,%M1 + ldb%: %0,%M1 + stb%: %1,%M0 + stb%: %1,%M0" [(set_attr "length" "4,4,4,8,4,4,4,4,8,4,8") (set_attr "type" "either,either,either,multi,mu,mu,either,sload,lload,mu,long")]) @@ -923,8 +929,8 @@ "" "@ # - ldb %0,%M1 - ldb %0,%M1" + ldb%: %0,%M1 + ldb%: %0,%M1" [(set_attr "type" "multi,sload,lload") (set_attr "length" "16,4,8")]) @@ -950,8 +956,8 @@ "" "@ # - ldb %0,%M1 - ldb %0,%M1" + ldb%: %0,%M1 + ldb%: %0,%M1" [(set_attr "type" "multi,sload,lload") (set_attr "length" "16,4,8")]) @@ -977,8 +983,8 @@ "" "@ # - ldh %0,%M1 - ldh %0,%M1" + ldh%: %0,%M1 + ldh%: %0,%M1" [(set_attr "type" "multi,sload,lload") (set_attr "length" "16,4,8")]) @@ -1062,9 +1068,9 @@ (zero_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))] "" "@ - and %0,%1,0xff - ldbu %0,%M1 - ldbu %0,%M1" + and%: %0,%1,0xff + ldbu%: %0,%M1 + ldbu%: %0,%M1" [(set_attr "length" "8,4,8") (set_attr "type" "long,sload,lload")]) @@ -1073,9 +1079,9 @@ (zero_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))] "" "@ - and %0,%1,0xff - ldbu %0,%M1 - ldbu %0,%M1" + and%: %0,%1,0xff + ldbu%: %0,%M1 + ldbu%: %0,%M1" [(set_attr "length" "8,4,8") (set_attr "type" "long,sload,lload")]) @@ -1084,9 +1090,9 @@ (zero_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m")))] "" "@ - and %0,%1,0xffff - ldhu %0,%M1 - ldhu %0,%M1" + and%: %0,%1,0xffff + ldhu%: %0,%M1 + ldhu%: %0,%M1" [(set_attr "length" "8,4,8") (set_attr "type" "long,sload,lload")]) @@ -1178,7 +1184,7 @@ (clobber (match_operand:CC 4 "flag_operand" "=f,f")) (clobber (match_operand:CC 5 "flag_operand" "=f,f"))] "" - "add %0,%1,%2" + "add%: %0,%1,%2" [(set_attr "length" "4,8") (set_attr "type" "either,long")]) @@ -1207,10 +1213,10 @@ (clobber (match_operand:CC 5 "flag_operand" "=f,f,f,f"))] "" "@ - sub %0,%1,%2 - sub %0,%1,%2 - sub %0,%.,%2 - sub %0,%.,%2" + sub%: %0,%1,%2 + sub%: %0,%1,%2 + sub%: %0,%.,%2 + sub%: %0,%.,%2" [(set_attr "length" "4,8,4,8") (set_attr "type" "either,long,either,long")]) @@ -1220,7 +1226,7 @@ (mult:SI (match_operand:SI 1 "gpr_operand" "%d") (match_operand:SI 2 "gpr_or_signed6_operand" "dI")))] "" - "mul %0,%1,%2" + "mul%: %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -1230,7 +1236,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "d")) (sign_extend:DI (match_operand:SI 2 "gpr_operand" "d"))))] "" - "mulx %0,%1,%2" + "mulx%: %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -1239,7 +1245,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "%d")) (match_operand:DI 2 "signed6_operand" "I")))] "" - "mulx %0,%1,%2" + "mulx%: %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -1273,8 +1279,8 @@ (const_int 32))))] "" "@ - or %0,%.,%U1 - mvfacc %0,%1,32" + or%: %0,%.,%U1 + mvfacc%: %0,%1,32" [(set_attr "length" "4") (set_attr "type" "either,iu")]) @@ -1300,7 +1306,7 @@ (clobber (match_operand:CC 3 "flag_operand" "=f")) (clobber (match_operand:CC 4 "flag_operand" "=f"))] "" - "sub %0,%.,%1" + "sub%: %0,%.,%1" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -1309,7 +1315,7 @@ [(set (match_operand:SI 0 "gpr_operand" "=d") (abs:SI (match_operand:SI 1 "gpr_operand" "d")))] "" - "abs %0,%1" + "abs%: %0,%1" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -1358,7 +1364,7 @@ (clobber (match_operand:CC 4 "flag_operand" "=f,f")) (clobber (match_operand:CC 5 "flag_operand" "=f,f"))] "" - "add %0,%1,%2" + "add%: %0,%1,%2" [(set_attr "length" "4,8") (set_attr "type" "scarry,lcarry")]) @@ -1370,7 +1376,7 @@ (clobber (match_operand:CC 4 "flag_operand" "=f,f")) (clobber (match_operand:CC 5 "flag_operand" "=f,f"))] "" - "addc %0,%1,%2" + "addc%: %0,%1,%2" [(set_attr "length" "4,8") (set_attr "type" "scarry,lcarry")]) @@ -1439,10 +1445,10 @@ (clobber (match_operand:CC 5 "flag_operand" "=f,f,f,f"))] "" "@ - sub %0,%1,%2 - sub %0,%1,%2 - sub %0,%.,%2 - sub %0,%.,%2" + sub%: %0,%1,%2 + sub%: %0,%1,%2 + sub%: %0,%.,%2 + sub%: %0,%.,%2" [(set_attr "length" "4,8,4,8") (set_attr "type" "scarry,lcarry,scarry,lcarry")]) @@ -1455,10 +1461,10 @@ (clobber (match_operand:CC 5 "flag_operand" "=f,f,f,f"))] "" "@ - subb %0,%1,%2 - subb %0,%1,%2 - subb %0,%.,%2 - subb %0,%.,%2" + subb%: %0,%1,%2 + subb%: %0,%1,%2 + subb%: %0,%.,%2 + subb%: %0,%.,%2" [(set_attr "length" "4,8,4,8") (set_attr "type" "scarry,lcarry,scarry,lcarry")]) @@ -1563,7 +1569,7 @@ (ashift:SI (match_operand:SI 1 "gpr_operand" "d") (match_operand:SI 2 "unsigned5_operand" "J")))] "" - "sra %0,%1,%n2" + "sra%: %0,%1,%n2" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -1572,7 +1578,7 @@ (ashift:SI (match_operand:SI 1 "gpr_operand" "d") (neg:SI (match_operand:SI 2 "gpr_operand" "d"))))] "" - "sra %0,%1,%2" + "sra%: %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -1582,7 +1588,7 @@ (ashiftrt:SI (match_operand:SI 1 "gpr_operand" "d") (match_operand:SI 2 "gpr_or_unsigned5_operand" "dJ")))] "" - "sra %0,%1,%2" + "sra%: %0,%1,%2" [(set_attr "length" "4")]) ;; Logical Shift Right @@ -1591,7 +1597,7 @@ (lshiftrt:SI (match_operand:SI 1 "gpr_operand" "d") (match_operand:SI 2 "gpr_or_unsigned5_operand" "dJ")))] "" - "srl %0,%1,%2" + "srl%: %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -1612,7 +1618,7 @@ (rotate:SI (match_operand:SI 1 "gpr_operand" "d") (match_operand:SI 2 "unsigned5_operand" "J")))] "" - "rot %0,%1,%n2" + "rot%: %0,%1,%n2" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -1621,7 +1627,7 @@ (rotate:SI (match_operand:SI 1 "gpr_operand" "d") (neg:SI (match_operand:SI 2 "gpr_operand" "d"))))] "" - "rot %0,%1,%2" + "rot%: %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -1631,7 +1637,7 @@ (rotatert:SI (match_operand:SI 1 "gpr_operand" "d") (match_operand:SI 2 "gpr_or_unsigned5_operand" "dJ")))] "" - "rot %0,%1,%2" + "rot%: %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -1671,8 +1677,8 @@ (match_operand:SI 2 "unsigned6_operand" "J,P")))] "" "@ - src %U0,%L0,%n2\;sra %L0,%L0,%n2 - sra %U0,%L1,%s2\;or %L0,%.,0" + src%: %U0,%L0,%n2\;sra%: %L0,%L0,%n2 + sra%: %U0,%L1,%s2\;or%: %L0,%.,0" [(set_attr "length" "8") (set_attr "type" "multi")]) @@ -1684,7 +1690,9 @@ "" "cmpge %3,%2,-31\;src%T3 %U0,%L0,%2\;sra%T3 %L0,%L0,%2\;sub%F3 %U0,%2,-32\;sra%F3 %U0,%L0,%U0\;or%F3 %L0,%.,0" [(set_attr "length" "32") - (set_attr "type" "multi")]) + (set_attr "type" "multi") + ;; Not strictly true, since we ought to be able to combine conditions, + (set_attr "predicable" "no")]) ;; Arithmetic Shift Right (define_insn "ashrdi3" @@ -1698,7 +1706,9 @@ sra %L0,%U1,%S2\;sra %U0,%L0,31 cmple %3,%2,31\;src%T3 %L0,%U0,%2\;sra%T3 %U0,%U0,%2\;add%F3 %L0,%2,-32\;sra%F3 %L0,%U0,%L0\;sra%F3 %U0,%U0,31" [(set_attr "length" "8,8,28") - (set_attr "type" "multi")]) + (set_attr "type" "multi") + ;; Not strictly true, since we ought to be able to combine conditions, + (set_attr "predicable" "no")]) ;; Logical Shift Right @@ -1713,7 +1723,9 @@ srl %L0,%U1,%S2\;or %U0,%.,0 cmple %3,%2,31\;src%T3 %L0,%U0,%2\;srl%T3 %U0,%U0,%2\;add%F3 %L0,%2,-32\;srl%F3 %L0,%U0,%L0\;or%F3 %U0,%.,0" [(set_attr "length" "8,8,28") - (set_attr "type" "multi")]) + (set_attr "type" "multi") + ;; Not strictly true, since we ought to be able to combine conditions, + (set_attr "predicable" "no")]) ;; :::::::::::::::::::: @@ -1723,112 +1735,56 @@ ;; :::::::::::::::::::: ;; Logical AND, 32 bit integers -(define_expand "andsi3" - [(set (match_operand:SI 0 "gpr_operand" "") - (and:SI (match_operand:SI 1 "gpr_operand" "") - (match_operand:SI 2 "gpr_or_constant_operand" "")))] - "" - "") -(define_insn "*andsi3_register" - [(set (match_operand:SI 0 "gpr_operand" "=d") - (and:SI (match_operand:SI 1 "gpr_operand" "%d") - (match_operand:SI 2 "gpr_operand" "d")))] - "" - "and %0,%1,%2" - [(set_attr "length" "4") - (set_attr "type" "either")]) - -(define_insn "*andsi3_move" - [(set (match_operand:SI 0 "gpr_operand" "=d,d") - (and:SI (match_operand:SI 1 "gpr_operand" "%0,d") - (match_operand:SI 2 "const_int_operand" "n,n")))] - "((INTVAL (operands[2]) & 0xffffffff) == 0xffffffff)" - "@ - ; and 0xffffffff to same register - and %0,%1,-1" - [(set_attr "length" "0,4") - (set_attr "type" "either")]) - -(define_insn "*andsi3_constant" +(define_insn "andsi3" [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d") (and:SI (match_operand:SI 1 "gpr_operand" "%d,d,d,d") - (match_operand:SI 2 "const_int_operand" "L,O,I,i")))] + (match_operand:SI 2 "gpr_or_constant_operand" "L,I,i,d")))] "" "@ - bclr %0,%1,%B2 - or %0,%.,0 - and %0,%1,%2 - and %0,%1,%2" - [(set_attr "length" "4,4,4,8") - (set_attr "type" "either,either,either,long")]) + bclr%: %0,%1,%B2 + and%: %0,%1,%2 + and%: %0,%1,%2 + and%: %0,%1,%2" + [(set_attr "length" "4,4,8,4") + (set_attr "type" "either,either,long,either")]) ;; Inclusive OR, 32 bit integers -(define_expand "iorsi3" - [(set (match_operand:SI 0 "gpr_operand" "") - (ior:SI (match_operand:SI 1 "gpr_operand" "") - (match_operand:SI 2 "gpr_or_constant_operand" "")))] - "" - "") -(define_insn "*iorsi3_register" - [(set (match_operand:SI 0 "gpr_operand" "=d") - (ior:SI (match_operand:SI 1 "gpr_operand" "%d") - (match_operand:SI 2 "gpr_operand" "d")))] - "" - "or %0,%1,%2" - [(set_attr "length" "4") - (set_attr "type" "either")]) - -(define_insn "*iorsi3_constant" +(define_insn "iorsi3" [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d") - (ior:SI (match_operand:SI 1 "gpr_operand" "%d,0,d,d") - (match_operand:SI 2 "const_int_operand" "K,O,I,i")))] + (ior:SI (match_operand:SI 1 "gpr_operand" "%d,d,d,d") + (match_operand:SI 2 "gpr_or_constant_operand" "K,I,i,d")))] "" "@ - bset %0,%1,%B2 - ; or 0 to same register (%0) - or %0,%1,%2 - or %0,%1,%2" - [(set_attr "length" "4,0,4,8") - (set_attr "type" "either,either,either,long")]) + bset%: %0,%1,%B2 + or%: %0,%1,%2 + or%: %0,%1,%2 + or%: %0,%1,%2" + [(set_attr "length" "4,4,8,4") + (set_attr "type" "either,either,long,either")]) ;; Exclusive OR, 32 bit integers -(define_expand "xorsi3" - [(set (match_operand:SI 0 "gpr_operand" "") - (xor:SI (match_operand:SI 1 "gpr_operand" "") - (match_operand:SI 2 "gpr_or_constant_operand" "")))] - "" - "") - -(define_insn "*xorsi3_register" - [(set (match_operand:SI 0 "gpr_operand" "=d") - (xor:SI (match_operand:SI 1 "gpr_operand" "%d") - (match_operand:SI 2 "gpr_operand" "d")))] - "" - "xor %0,%1,%2" - [(set_attr "length" "4") - (set_attr "type" "either")]) (define_insn "*xorsi3_constant" [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d") - (xor:SI (match_operand:SI 1 "gpr_operand" "%d,0,d,d") - (match_operand:SI 2 "const_int_operand" "K,O,I,i")))] + (xor:SI (match_operand:SI 1 "gpr_operand" "%d,d,d,d") + (match_operand:SI 2 "gpr_or_constant_operand" "K,I,i,d")))] "" "@ - bnot %0,%1,%B2 - ; xor 0 to same register (%0) - xor %0,%1,%2 - xor %0,%1,%2" - [(set_attr "length" "4,0,4,8") - (set_attr "type" "either,either,either,long")]) + bnot%: %0,%1,%B2 + xor%: %0,%1,%2 + xor%: %0,%1,%2 + xor%: %0,%1,%2" + [(set_attr "length" "4,4,8,4") + (set_attr "type" "either,either,long,either")]) ;; One's complement, 32 bit integers (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "gpr_operand" "=d") (not:SI (match_operand:SI 1 "gpr_operand" "d")))] "" - "not %0,%1" + "not%: %0,%1" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -1945,7 +1901,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "%d")) (sign_extend:DI (match_operand:SI 2 "gpr_operand" "d")))))] "" - "mac%A0 %.,%1,%2" + "mac%A0%: %.,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -1955,7 +1911,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "%d")) (match_operand:DI 2 "signed6_operand" "I"))))] "" - "mac%A0 %.,%1,%2" + "mac%A0%: %.,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -1966,7 +1922,7 @@ (sign_extend:DI (match_operand:SI 2 "gpr_operand" "d"))) (const_int 1))))] "" - "macs%A0 %.,%1,%2" + "macs%A0%: %.,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -1977,7 +1933,7 @@ (match_operand:DI 2 "signed6_operand" "I")) (const_int 1))))] "" - "macs%A0 %.,%1,%2" + "macs%A0%: %.,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -1987,7 +1943,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "d")) (sign_extend:DI (match_operand:SI 2 "gpr_operand" "d")))))] "" - "msub%A0 %.,%1,%2" + "msub%A0%: %.,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -1997,7 +1953,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "d")) (match_operand:DI 2 "signed6_operand" "I"))))] "" - "msub%A0 %.,%1,%2" + "msub%A0%: %.,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -2008,7 +1964,7 @@ (sign_extend:DI (match_operand:SI 2 "gpr_operand" "d"))) (const_int 1))))] "" - "msubs%A0 %.,%1,%2" + "msubs%A0%: %.,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -2019,7 +1975,7 @@ (match_operand:DI 2 "signed6_operand" "I")) (const_int 1))))] "" - "msubs%A0 %.,%1,%2" + "msubs%A0%: %.,%1,%2" [(set_attr "length" "4") (set_attr "type" "mul")]) @@ -2067,7 +2023,7 @@ [(match_operand:SI 2 "gpr_operand" "d,d") (match_operand:SI 3 "gpr_or_constant_operand" "dI,i")]))] "" - "%R1 %0,%2,%3" + "%R1%: %0,%2,%3" [(set_attr "length" "4,8") (set_attr "type" "scmp,lcmp")]) @@ -2077,7 +2033,7 @@ [(match_operand:SI 2 "gpr_operand" "d,d") (match_operand:SI 3 "gpr_or_constant_operand" "dJP,i")]))] "" - "%R1 %0,%2,%3" + "%R1%: %0,%2,%3" [(set_attr "length" "4,8") (set_attr "type" "scmp,lcmp")]) @@ -2093,7 +2049,8 @@ "" "%R3%T1 %0,%4,%5" [(set_attr "length" "4,8") - (set_attr "type" "scmp,lcmp")]) + (set_attr "type" "scmp,lcmp") + (set_attr "predicable" "no")]) (define_insn "*movcccc_signed_false" [(set (match_operand:CC 0 "flag_operand" "=f,f") @@ -2105,7 +2062,8 @@ "" "%R3%F1 %0,%4,%5" [(set_attr "length" "4,8") - (set_attr "type" "scmp,lcmp")]) + (set_attr "type" "scmp,lcmp") + (set_attr "predicable" "no")]) (define_insn "*movcccc_unsigned_true" [(set (match_operand:CC 0 "flag_operand" "=f,f") @@ -2117,7 +2075,8 @@ "" "%R3%T1 %0,%4,%5" [(set_attr "length" "4,8") - (set_attr "type" "scmp,lcmp")]) + (set_attr "type" "scmp,lcmp") + (set_attr "predicable" "no")]) (define_insn "*movcccc_unsigned_false" [(set (match_operand:CC 0 "flag_operand" "=f,f") @@ -2129,7 +2088,8 @@ "" "%R3%F1 %0,%4,%5" [(set_attr "length" "4,8") - (set_attr "type" "scmp,lcmp")]) + (set_attr "type" "scmp,lcmp") + (set_attr "predicable" "no")]) ;; 64 bit integer tests (define_insn "*eqdi_internal" @@ -2193,7 +2153,7 @@ (lt:CC (match_operand:DI 1 "gpr_operand" "e") (const_int 0)))] "" - "cmplt %0,%U1,0" + "cmplt%: %0,%U1,0" [(set_attr "length" "4") (set_attr "type" "scmp")]) @@ -2232,7 +2192,7 @@ (ge:CC (match_operand:DI 1 "gpr_operand" "e") (const_int 0)))] "" - "cmpge %0,%U1,0" + "cmpge%: %0,%U1,0" [(set_attr "length" "4") (set_attr "type" "scmp")]) @@ -2530,7 +2490,8 @@ return \"; jump to %l0 optimized away\"; }" - [(set_attr "type" "br")]) + [(set_attr "type" "br") + (set_attr "predicable" "no")]) (define_insn "*bra_false" [(set (pc) @@ -2554,7 +2515,8 @@ return \"; jump to %l0 optimized away\"; }" - [(set_attr "type" "br")]) + [(set_attr "type" "br") + (set_attr "predicable" "no")]) ;; Peephole to turn set flag, cond. jumps into branch if register ==/!= 0. @@ -2569,7 +2531,9 @@ (const_int 0)]) (match_operand 4 "" "") (match_operand 5 "" "")))] - "reg_dead_p (last_insn, operands[0])" + "peep2_reg_dead_p (2, operands[0]) + && GET_CODE (operands[4]) != RETURN + && GET_CODE (operands[5]) != RETURN" [(set (pc) (if_then_else (match_dup 6) (match_dup 4) @@ -2596,7 +2560,8 @@ { return GET_CODE (operands[1]) == NE ? \"bratnz %2,%l0\" : \"bratzr %2,%l0\"; }" - [(set_attr "type" "br2")]) + [(set_attr "type" "br2") + (set_attr "predicable" "no")]) (define_insn "*bra_reg_false" [(set (pc) (if_then_else (match_operator:CC 1 "branch_zero_operator" @@ -2609,7 +2574,8 @@ { return GET_CODE (operands[1]) == EQ ? \"bratnz %2,%l0\" : \"bratzr %2,%l0\"; }" - [(set_attr "type" "br2")]) + [(set_attr "type" "br2") + (set_attr "predicable" "no")]) ;; :::::::::::::::::::: ;; :: @@ -2767,8 +2733,8 @@ "" "@ # - mvfsys %0,%1 - or %0,%.,%1" + mvfsys%: %0,%1 + or%: %0,%.,%1" [(set_attr "length" "8,4,4") (set_attr "type" "multi,either,either")]) @@ -2798,7 +2764,7 @@ (and:CC (match_operand:CC 1 "flag_operand" "f") (match_operand:CC 2 "flag_operand" "f")))] "" - "andfg %0,%1,%2" + "andfg%: %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -2807,7 +2773,7 @@ (ior:CC (match_operand:CC 1 "flag_operand" "f") (match_operand:CC 2 "flag_operand" "f")))] "" - "orfg %0,%1,%2" + "orfg%: %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -2816,7 +2782,7 @@ (xor:CC (match_operand:CC 1 "flag_operand" "f") (match_operand:CC 2 "flag_operand" "f")))] "" - "xorfg %0,%1,%2" + "xorfg%: %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "either")]) @@ -2829,8 +2795,10 @@ (match_operand:SI 2 "gpr_operand" "0")))] "" "add%T1 %0,%2,1" -[(set_attr "length" "4") - (set_attr "type" "either")]) + [(set_attr "length" "4") + (set_attr "type" "either") + ;; Not strictly true -- we could combine conditions. + (set_attr "predicable" "no")]) (define_insn "decscc" [(set (match_operand:SI 0 "gpr_operand" "=d") @@ -2839,8 +2807,10 @@ (const_int 1))))] "" "sub%T2 %0,%1,1" -[(set_attr "length" "4") - (set_attr "type" "either")]) + [(set_attr "length" "4") + (set_attr "type" "either") + ;; Not strictly true -- we could combine conditions. + (set_attr "predicable" "no")]) ;; :::::::::::::::::::: ;; :: @@ -2882,8 +2852,8 @@ (clobber (match_operand 3 "" "=d,d"))] "" "@ - jsr %0 - bsr %0" + jsr%: %0 + bsr%: %0" [(set_attr "length" "4,8") (set_attr "type" "mu,long")]) @@ -2920,8 +2890,8 @@ (clobber (match_operand 4 "" "=d,d"))] "" "@ - jsr %1 - bsr %1" + jsr%: %1 + bsr%: %1" [(set_attr "length" "4,8") (set_attr "type" "mu,long")]) @@ -2936,7 +2906,8 @@ "reload_completed" "jmp link" [(set_attr "length" "4") - (set_attr "type" "mu")]) + (set_attr "type" "mu") + (set_attr "predicable" "no")]) (define_insn "*cond_return_true" [(set (pc) @@ -2948,7 +2919,8 @@ "reload_completed" "jmp%F0 link" [(set_attr "length" "4") - (set_attr "type" "mu")]) + (set_attr "type" "mu") + (set_attr "predicable" "no")]) (define_insn "*cond_return_false" [(set (pc) @@ -2960,14 +2932,16 @@ "reload_completed" "jmp%T0 link" [(set_attr "length" "4") - (set_attr "type" "mu")]) + (set_attr "type" "mu") + (set_attr "predicable" "no")]) ;; Normal unconditional jump (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "bra %l0" - [(set_attr "type" "br")]) + [(set_attr "type" "br") + (set_attr "predicable" "no")]) ;; Indirect jump through a register (define_insn "indirect_jump" @@ -2975,7 +2949,8 @@ "" "jmp %0" [(set_attr "length" "4") - (set_attr "type" "mu")]) + (set_attr "type" "mu") + (set_attr "predicable" "no")]) ;; Instruction to jump to a variable address. This is a low-level capability ;; which can be used to implement a dispatch table when there is no `casesi' @@ -2998,7 +2973,8 @@ "" "jmp %0" [(set_attr "length" "4") - (set_attr "type" "mu")]) + (set_attr "type" "mu") + (set_attr "predicable" "no")]) @@ -3101,7 +3077,8 @@ "" "#" [(set_attr "length" "4,8,4,8,4,4,4,8,4,8,4,4,16") - (set_attr "type" "either,long,sload,lload,mu,mu,either,long,sload,lload,mu,mu,multi")]) + (set_attr "type" "either,long,sload,lload,mu,mu,either,long,sload,lload,mu,mu,multi") + (set_attr "predicable" "no")]) ;; If we have: a = (test) ? a : b, or a = (test) ? b : a, we can split it ;; before reload to allow combine to substitute in early. @@ -3181,7 +3158,8 @@ "" "#" [(set_attr "length" "4,8,4,8,4,4,4,8,4,8,4,4,16") - (set_attr "type" "either,long,sload,lload,mu,mu,either,long,sload,lload,mu,mu,multi")]) + (set_attr "type" "either,long,sload,lload,mu,mu,either,long,sload,lload,mu,mu,multi") + (set_attr "predicable" "no")]) ;; If we have: a = (test) ? a : b, or a = (test) ? b : a, we can split it ;; before reload to allow combine to substitute in early. @@ -3261,7 +3239,8 @@ "" "#" [(set_attr "length" "4,8,4,8,4,4,4,8,4,8,4,4,16") - (set_attr "type" "either,long,sload,lload,mu,mu,either,long,sload,lload,mu,mu,multi")]) + (set_attr "type" "either,long,sload,lload,mu,mu,either,long,sload,lload,mu,mu,multi") + (set_attr "predicable" "no")]) ;; If we have: a = (test) ? a : b, or a = (test) ? b : a, we can split it ;; before reload to allow combine to substitute in early. @@ -3341,7 +3320,8 @@ "" "#" [(set_attr "length" "4,8,4,8,4,8,4,8,16") - (set_attr "type" "either,long,sload,lload,either,long,sload,lload,multi")]) + (set_attr "type" "either,long,sload,lload,either,long,sload,lload,multi") + (set_attr "predicable" "no")]) (define_split [(set (match_operand:SF 0 "move_output_operand" "") @@ -3393,373 +3373,6 @@ operands[5] = gen_rtx_EQ (CCmode, operands[2], const0_rtx); }") - -;; :::::::::::::::::::: -;; :: -;; :: Conditional execution -;; :: -;; :::::::::::::::::::: - -(define_insn "*cond_exec_movqi" - [(cond_exec - (match_operator:CC 2 "condexec_test_operator" - [(match_operand:CC 3 "br_flag_operand" "b,b,b,b,b,b,b,b,b,b") - (const_int 0)]) - (set (match_operand:QI 0 "move_output_operand" "=d,d,d,d,Q,m,Q,m,d,c") - (match_operand:QI 1 "move_input_operand" "dI,i,Q,m,d,d,O,O,c,d")))] - "register_operand (operands[0], QImode) - || reg_or_0_operand (operands[1], QImode)" - "@ - or%F2 %0,%.,%1 - or%F2 %0,%.,%1 - ldb%F2 %0,%M1 - ldb%F2 %0,%M1 - stb%F2 %1,%M0 - stb%F2 %1,%M0 - stb%F2 %.,%M0 - stb%F2 %.,%M0 - mvfsys%F2 %0,%1 - mvtsys%F2 %0,%1" - [(set_attr "length" "4,8,4,8,4,8,4,8,4,4") - (set_attr "type" "either,long,sload,lload,mu,long,mu,long,mu,mu")]) - -(define_insn "*cond_exec_movhi" - [(cond_exec - (match_operator:CC 2 "condexec_test_operator" - [(match_operand:CC 3 "br_flag_operand" "b,b,b,b,b,b,b,b,b,b") - (const_int 0)]) - (set (match_operand:HI 0 "move_output_operand" "=d,d,d,d,Q,m,Q,m,d,c") - (match_operand:HI 1 "move_input_operand" "dI,i,Q,m,d,d,O,O,c,d")))] - "register_operand (operands[0], HImode) - || reg_or_0_operand (operands[1], HImode)" - "@ - or%F2 %0,%.,%1 - or%F2 %0,%.,%1 - ldh%F2 %0,%M1 - ldh%F2 %0,%M1 - sth%F2 %1,%M0 - sth%F2 %1,%M0 - sth%F2 %.,%M0 - sth%F2 %.,%M0 - mvfsys%F2 %0,%1 - mvtsys%F2 %0,%1" - [(set_attr "length" "4,8,4,8,4,8,4,8,4,4") - (set_attr "type" "either,long,sload,lload,mu,long,mu,long,mu,mu")]) - -(define_insn "*cond_exec_movsi" - [(cond_exec - (match_operator:CC 2 "condexec_test_operator" - [(match_operand:CC 3 "br_flag_operand" "b,b,b,b,b,b,b,b,b,b,b") - (const_int 0)]) - (set (match_operand:SI 0 "move_output_operand" "=d,d,d,d,d,Q,m,Q,m,d,c") - (match_operand:SI 1 "move_input_operand" "dI,F,i,Q,m,d,d,O,O,c,d")))] - "register_operand (operands[0], SImode) - || reg_or_0_operand (operands[1], SImode)" - "@ - or%F2 %0,%.,%1 - or%F2 %0,%.,%L1 - or%F2 %0,%.,%1 - ldw%F2 %0,%M1 - ldw%F2 %0,%M1 - stw%F2 %1,%M0 - stw%F2 %1,%M0 - stw%F2 %.,%M0 - stw%F2 %.,%M0 - mvfsys%F2 %0,%1 - mvtsys%F2 %0,%1" - [(set_attr "length" "4,8,8,4,8,4,8,4,8,4,4") - (set_attr "type" "either,long,long,sload,lload,mu,long,mu,long,mu,mu")]) - -(define_insn "*cond_exec_movsf" - [(cond_exec - (match_operator:CC 2 "condexec_test_operator" - [(match_operand:CC 3 "br_flag_operand" "b,b,b,b,b,b,b,b,b") - (const_int 0)]) - (set (match_operand:SF 0 "move_output_operand" "=d,d,d,d,d,Q,m,Q,m") - (match_operand:SF 1 "move_input_operand" "d,G,F,Q,m,d,d,G,G")))] - "register_operand (operands[0], SFmode) - || reg_or_0_operand (operands[1], SFmode)" - "@ - or%F2 %0,%.,%1 - or%F2 %0,%.,0 - or%F2 %0,%.,%f1 - ldw%F2 %0,%M1 - ldw%F2 %0,%M1 - stw%F2 %1,%M0 - stw%F2 %1,%M0 - stw%F2 %.,%M0 - stw%F2 %.,%M0" - [(set_attr "length" "4,4,8,4,8,4,8,4,8") - (set_attr "type" "either,either,long,sload,lload,mu,long,mu,long")]) - -(define_insn "*cond_exec_zero_extendqisi" - [(cond_exec - (match_operator 2 "condexec_test_operator" - [(match_operand:CC 3 "br_flag_operand" "b,b,b") - (const_int 0)]) - (set (match_operand:SI 0 "gpr_operand" "=d,d,d") - (zero_extend:SI - (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m"))))] - "" - "@ - and%F2 %0,%1,0xff - ldbu%F2 %0,%M1 - ldbu%F2 %0,%M1" - [(set_attr "length" "8,4,8") - (set_attr "type" "long,sload,lload")]) - -(define_insn "*cond_exec_sign_extendqisi" - [(cond_exec - (match_operator 2 "condexec_test_operator" - [(match_operand:CC 3 "br_flag_operand" "b,b,b") - (const_int 0)]) - (set (match_operand:SI 0 "gpr_operand" "=d,d,d") - (sign_extend:SI - (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m"))))] - "" - "@ - # - ldbu%F2 %0,%M1 - ldbu%F2 %0,%M1" - [(set_attr "length" "8,4,8") - (set_attr "type" "multi,sload,lload")]) - -(define_split - [(cond_exec - (match_operator 1 "condexec_test_operator" - [(match_operand:CC 2 "br_flag_operand" "") - (const_int 0)]) - (set (match_operand:SI 0 "gpr_operand" "") - (sign_extend:SI (match_operand:QI 3 "gpr_operand" ""))))] - "reload_completed" - [(cond_exec (match_dup 1) - (set (match_dup 5) (ashift:SI (match_dup 6) (const_int 24)))) - (cond_exec (match_dup 1) - (set (match_dup 5) (ashiftrt:SI (match_dup 5) (const_int 24))))] - " -{ - operands[5] = gen_lowpart (SImode, operands[0]); - operands[6] = gen_lowpart (SImode, operands[1]); -}") - -(define_insn "*cond_exec_zero_extendhisi" - [(cond_exec - (match_operator 2 "condexec_test_operator" - [(match_operand:CC 3 "br_flag_operand" "b,b,b") - (const_int 0)]) - (set (match_operand:SI 0 "gpr_operand" "=d,d,d") - (zero_extend:SI - (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m"))))] - "" - "@ - and%F2 %0,%1,0xffff - ldbu%F2 %0,%M1 - ldbu%F2 %0,%M1" - [(set_attr "length" "8,4,8") - (set_attr "type" "long,sload,lload")]) - -(define_insn "*cond_exec_sign_extendhisi" - [(cond_exec - (match_operator 2 "condexec_test_operator" - [(match_operand:CC 3 "br_flag_operand" "b,b,b") - (const_int 0)]) - (set (match_operand:SI 0 "gpr_operand" "=d,d,d") - (sign_extend:SI - (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m"))))] - "" - "@ - # - ldbu%F2 %0,%M1 - ldbu%F2 %0,%M1" - [(set_attr "length" "8,4,8") - (set_attr "type" "multi,sload,lload")]) - -(define_split - [(cond_exec - (match_operator 2 "condexec_test_operator" - [(match_operand:CC 3 "br_flag_operand" "") - (const_int 0)]) - (set (match_operand:SI 0 "gpr_operand" "") - (sign_extend:SI (match_operand:HI 1 "gpr_operand" ""))))] - "reload_completed" - [(cond_exec (match_dup 1) - (set (match_dup 5) (ashift:SI (match_dup 6) (const_int 16)))) - (cond_exec (match_dup 1) - (set (match_dup 5) (ashiftrt:SI (match_dup 5) (const_int 16))))] - " -{ - operands[5] = gen_lowpart (SImode, operands[0]); - operands[6] = gen_lowpart (SImode, operands[3]); -}") - -(define_insn "*cond_exec_si_unary" - [(cond_exec - (match_operator 3 "condexec_test_operator" - [(match_operand:CC 4 "br_flag_operand" "b") - (const_int 0)]) - (set (match_operand:SI 0 "gpr_operand" "=d") - (match_operator:SI 1 "condexec_unary_operator" - [(match_operand:SI 2 "gpr_operand" "d")])))] - "" - "* -{ - switch (GET_CODE (operands[1])) - { - default: - fatal_insn (\"cond_exec_si_unary:\", insn); - - case ABS: return \"abs%F3 %0,%2\"; - case NOT: return \"not%F3 %0,%2\"; - } -}" - [(set_attr "length" "4") - (set_attr "type" "either")]) - -(define_insn "*cond_exec_si_neg" - [(cond_exec - (match_operator 2 "condexec_test_operator" - [(match_operand:CC 3 "br_flag_operand" "b") - (const_int 0)]) - (parallel [ - (set (match_operand:SI 0 "gpr_operand" "=d") - (neg:SI (match_operand:SI 1 "gpr_operand" "d"))) - (clobber (match_operand:CC 4 "flag_operand" "")) - (clobber (match_operand:CC 5 "flag_operand" "")) - (clobber (match_operand:CC 6 "flag_operand" ""))]))] - "" - "sub%F2 %0,%.,%1" - [(set_attr "length" "4") - (set_attr "type" "either")]) - -(define_insn "*cond_exec_si_addsub" - [(cond_exec - (match_operator 4 "condexec_test_operator" - [(match_operand:CC 5 "br_flag_operand" "b,b") - (const_int 0)]) - (parallel [ - (set (match_operand:SI 0 "gpr_operand" "=d,d") - (match_operator:SI 1 "condexec_addsub_operator" - [(match_operand:SI 2 "gpr_operand" "d,d") - (match_operand:SI 3 "gpr_or_constant_operand" "dI,i")])) - (clobber (match_operand:CC 6 "flag_operand" "")) - (clobber (match_operand:CC 7 "flag_operand" "")) - (clobber (match_operand:CC 8 "flag_operand" ""))]))] - "" - "* -{ - switch (GET_CODE (operands[1])) - { - default: - fatal_insn (\"cond_exec_si_addsub_true:\", insn); - - case PLUS: return \"add%F4 %0,%2,%3\"; - case MINUS: return \"sub%F4 %0,%2,%3\"; - } -}" - [(set_attr "length" "4,8") - (set_attr "type" "either,long")]) - -(define_insn "*cond_exec_si_binary" - [(cond_exec - (match_operator 4 "condexec_test_operator" - [(match_operand:CC 5 "br_flag_operand" "b,b") - (const_int 0)]) - (set (match_operand:SI 0 "gpr_operand" "=d,d") - (match_operator:SI 1 "condexec_binary_operator" - [(match_operand:SI 2 "gpr_operand" "d,d") - (match_operand:SI 3 "gpr_or_constant_operand" "dI,i")])))] - "" - "* -{ - switch (GET_CODE (operands[1])) - { - default: - fatal_insn (\"cond_exec_si_binary_true:\", insn); - - case AND: return \"and%F4 %0,%2,%3\"; - case IOR: return \"or%F4 %0,%2,%3\"; - case XOR: return \"xor%F4 %0,%2,%3\"; - case ASHIFT: return \"sra%F4 %0,%2,%n3\"; - case ASHIFTRT: return \"sra%F4 %0,%2,%3\"; - case LSHIFTRT: return \"srl%F4 %0,%2,%3\"; - case ROTATE: return \"rot%F4 %0,%2,%n3\"; - case ROTATERT: return \"rot%F4 %0,%2,%3\"; - } -}" - [(set_attr "length" "4,8") - (set_attr "type" "either,long")]) - -(define_insn "*cond_exec_si_shiftl" - [(cond_exec - (match_operator 4 "condexec_test_operator" - [(match_operand:CC 5 "br_flag_operand" "b") - (const_int 0)]) - (set (match_operand:SI 0 "gpr_operand" "=d") - (match_operator:SI 1 "condexec_shiftl_operator" - [(match_operand:SI 2 "gpr_operand" "d") - (neg:SI (match_operand:SI 3 "gpr_operand" "d"))])))] - "" - "* -{ - switch (GET_CODE (operands[1])) - { - default: - fatal_insn (\"cond_exec_si_shiftl_true:\", insn); - - case ASHIFT: return \"sra%F4 %0,%2,%3\"; - case ROTATE: return \"rot%F4 %0,%2,%3\"; - } -}" - [(set_attr "length" "4") - (set_attr "type" "either")]) - -(define_insn "*cond_exec_si_mul" - [(cond_exec - (match_operator 4 "condexec_test_operator" - [(match_operand:CC 5 "br_flag_operand" "b") - (const_int 0)]) - (set (match_operand:SI 0 "gpr_operand" "=d") - (mult:SI (match_operand:SI 1 "gpr_operand" "%d") - (match_operand:SI 2 "gpr_or_signed6_operand" "dI"))))] - "" - "mul%F4 %0,%1,%2" - [(set_attr "length" "4") - (set_attr "type" "iu")]) - -(define_insn "*cond_exec_call_internal" - [(cond_exec - (match_operator 4 "condexec_test_operator" - [(match_operand:CC 5 "br_flag_operand" "b,b") - (const_int 0)]) - (parallel [ - (call (match_operand:QI 0 "call_operand" "R,S") - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (match_operand 3 "" "=d,d"))]))] - "" - "@ - jsr%F4 %0 - bsr%F4 %0" - [(set_attr "length" "4,8") - (set_attr "type" "mu,long")]) - -(define_insn "*cond_exec_call_value_internal" - [(cond_exec - (match_operator 5 "condexec_test_operator" - [(match_operand:CC 6 "br_flag_operand" "b,b") - (const_int 0)]) - (parallel [ - (set (match_operand 0 "gpr_operand" "=d,d") - (call (match_operand:QI 1 "call_operand" "R,S") - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) - (clobber (match_operand 4 "" "=d,d"))]))] - "" - "@ - jsr%F5 %1 - bsr%F5 %1" - [(set_attr "length" "4,8") - (set_attr "type" "mu,long")]) ;; :::::::::::::::::::: ;; :: @@ -3773,7 +3386,8 @@ "" "nop || nop" [(set_attr "length" "8") - (set_attr "type" "long")]) + (set_attr "type" "long") + (set_attr "predicable" "no")]) ;; Pseudo instruction that prevents the scheduler from moving code above this ;; point. @@ -3782,4 +3396,18 @@ "" "" [(set_attr "length" "0") - (set_attr "type" "unknown")]) + (set_attr "type" "unknown") + (set_attr "predicable" "no")]) + +;; :::::::::::::::::::: +;; :: +;; :: Conditional execution +;; :: +;; :::::::::::::::::::: + +(define_cond_exec + [(match_operator:CC 0 "condexec_test_operator" + [(match_operand:CC 1 "br_flag_operand" "f") + (const_int 0)])] + "" + "")