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Add ALTIVEC_REGS as pressure class.

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Code that has heavy register pressure on Altivec registers can suffer from
over-aggressive scheduling during sched1, which then leads to increased
register spill. This is due to the fact that registers that prefer
ALTIVEC_REGS are currently assigned an allocno class of VSX_REGS. This then
misleads the scheduler to think there are 64 regs available, when in reality
there are only 32 Altivec regs. This patch fixes the problem by assigning an
allocno class of ALTIVEC_REGS and adding ALTIVEC_REGS as a pressure class.

2021-05-10  Pat Haugen  <pthaugen@linux.ibm.com>

gcc/ChangeLog:

	* config/rs6000/rs6000.c (rs6000_ira_change_pseudo_allocno_class):
	Return ALTIVEC_REGS if that is best_class.
	(rs6000_compute_pressure_classes): Add ALTIVEC_REGS.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/fold-vec-insert-float-p9.c: Adjust counts.
	* gcc.target/powerpc/vec-rlmi-rlnm.c: Likewise.
This commit is contained in:
Pat Haugen 2021-05-10 13:49:06 -05:00
parent e85f3aeddb
commit 51d89e61f7
3 changed files with 10 additions and 7 deletions
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11
gcc/config/rs6000/rs6000.c
View file

@ -22527,11 +22527,14 @@ rs6000_ira_change_pseudo_allocno_class (int regno ATTRIBUTE_UNUSED,
of allocno class. */
if (best_class == BASE_REGS)
return GENERAL_REGS;
if (TARGET_VSX
&& (best_class == FLOAT_REGS || best_class == ALTIVEC_REGS))
if (TARGET_VSX && best_class == FLOAT_REGS)
return VSX_REGS;
return best_class;
case VSX_REGS:
if (best_class == ALTIVEC_REGS)
return ALTIVEC_REGS;
default:
break;
}
@ -23649,12 +23652,12 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
n = 0;
pressure_classes[n++] = GENERAL_REGS;
if (TARGET_ALTIVEC)
pressure_classes[n++] = ALTIVEC_REGS;
if (TARGET_VSX)
pressure_classes[n++] = VSX_REGS;
else
{
if (TARGET_ALTIVEC)
pressure_classes[n++] = ALTIVEC_REGS;
if (TARGET_HARD_FLOAT)
pressure_classes[n++] = FLOAT_REGS;
}

4
gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c
View file

@ -31,5 +31,5 @@ testf_cst (float f, vector float vf)
/* { dg-final { scan-assembler-times {\mstfs\M} 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlxv\M} 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlvewx\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mvperm\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mxxperm\M} 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mvperm\M} 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mxxperm\M} 1 { target ilp32 } } } */

2
gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c
View file

@ -62,6 +62,6 @@ rlnm_test_2 (vector unsigned long long x, vector unsigned long long y,
/* { dg-final { scan-assembler-times "vextsb2d" 1 } } */
/* { dg-final { scan-assembler-times "vslw" 1 } } */
/* { dg-final { scan-assembler-times "vsld" 1 } } */
/* { dg-final { scan-assembler-times "xxlor" 3 } } */
/* { dg-final { scan-assembler-times "xxlor" 2 } } */
/* { dg-final { scan-assembler-times "vrlwnm" 2 } } */
/* { dg-final { scan-assembler-times "vrldnm" 2 } } */