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RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE

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The mode attr V_F2DI_CONVERT_BRIDGE converts the floating-point mode
to the widden floating-point by design. But we take (RVVM1HF "RVVM2SI") by
mistake.

This patch would like to fix it by replacing the
(RVVM1HF "RVVM2SI") to (RVVM1HF "RVVM2SF") as design.

gcc/ChangeLog:

	* config/riscv/vector-iterators.md: Replace RVVM2SI to RVVM2SF
	for mode attr V_F2DI_CONVERT_BRIDGE.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li 2023-12-08 14:48:48 +08:00
parent bf3ff057f6
commit 51b8259212
2 changed files with 8 additions and 1 deletions
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2
gcc/config/riscv/vector-iterators.md
View file

@ -3267,7 +3267,7 @@
])
(define_mode_attr V_F2DI_CONVERT_BRIDGE [
(RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SI") (RVVMF2HF "RVVM1SF")
(RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SF") (RVVMF2HF "RVVM1SF")
(RVVMF4HF "RVVMF2SF")
(RVVM4SF "VOID") (RVVM2SF "VOID") (RVVM1SF "VOID")

7
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c Normal file
View file

@ -0,0 +1,7 @@
/* Test that we do not have ice when compile */
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-lmul=m4 -march=rv64gcv_zvfh_zfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */
#include "test-math.h"
TEST_UNARY_CALL_CVT (_Float16, long, __builtin_lroundf16)