msp430.c (msp430_print_operand): Rename %B to %b and %A to %Q.
* config/msp430/msp430.c (msp430_print_operand): Rename %B to %b and %A to %Q. Add %A, %B, %C and %D as selectors for 16-bit parts of a 64-bit operand. * config/msp430/msp430.md: Replace uses of %B with %b and uses of %A with %q. From-SVN: r206247
This commit is contained in:
Nick Clifton
Nick Clifton
parent
c99ebd4dde
commit
51ac3042e7
3 changed files with 115 additions and 45 deletions
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@ -1,3 +1,11 @@
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2013-12-30 Nick Clifton <nickc@redhat.com>
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* config/msp430/msp430.c (msp430_print_operand): Rename %B to %b
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and %A to %Q. Add %A, %B, %C and %D as selectors for 16-bit parts
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of a 64-bit operand.
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* config/msp430/msp430.md: Replace uses of %B with %b and uses of
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%A with %q.
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2013-12-30 Felix Yang <felix.yang@huawei.com>
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* ira-costs.c (cost_classes_hasher::equal): Check equality of
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@ -1914,6 +1914,24 @@ msp430_print_operand_addr (FILE * file, rtx addr)
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#undef TARGET_PRINT_OPERAND
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#define TARGET_PRINT_OPERAND msp430_print_operand
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/* A low 16-bits of int/lower of register pair
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B high 16-bits of int/higher of register pair
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C bits 32-47 of a 64-bit value/reg 3 of a DImode value
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D bits 48-63 of a 64-bit value/reg 4 of a DImode value
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H like %B (for backwards compatibility)
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I inverse of value
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L like %A (for backwards compatibility)
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O offset of the top of the stack
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Q like X but generates an A postfix
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R inverse of condition code, unsigned.
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X X instruction postfix in large mode
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Y value - 4
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Z value - 1
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b .B or .W or .A, depending upon the mode
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p bit position
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r inverse of condition code
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x like X but only for pointers. */
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static void
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msp430_print_operand (FILE * file, rtx op, int letter)
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{
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@ -1978,7 +1996,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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gcc_assert (CONST_INT_P (op));
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fprintf (file, "#%d", 1 << INTVAL (op));
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return;
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case 'B':
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case 'b':
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switch (GET_MODE (op))
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{
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case QImode: fprintf (file, ".B"); return;
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@ -1988,6 +2006,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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default:
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return;
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}
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case 'A':
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case 'L': /* Low half. */
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switch (GET_CODE (op))
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{
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@ -2005,6 +2024,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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gcc_unreachable ();
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}
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break;
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case 'B':
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case 'H': /* high half */
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switch (GET_CODE (op))
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{
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@ -2023,6 +2043,42 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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gcc_unreachable ();
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}
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break;
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case 'C':
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switch (GET_CODE (op))
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{
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case MEM:
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op = adjust_address (op, Pmode, 3);
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break;
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case REG:
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op = gen_rtx_REG (Pmode, REGNO (op) + 2);
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break;
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case CONST_INT:
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op = GEN_INT (INTVAL (op) >> 32);
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letter = 0;
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break;
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default:
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/* If you get here, figure out a test case :-) */
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gcc_unreachable ();
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}
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break;
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case 'D':
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switch (GET_CODE (op))
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{
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case MEM:
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op = adjust_address (op, Pmode, 4);
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break;
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case REG:
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op = gen_rtx_REG (Pmode, REGNO (op) + 3);
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break;
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case CONST_INT:
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op = GEN_INT (INTVAL (op) >> 48);
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letter = 0;
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break;
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default:
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/* If you get here, figure out a test case :-) */
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gcc_unreachable ();
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}
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break;
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case 'X':
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/* This is used to turn, for example, an ADD opcode into an ADDX
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@ -2039,7 +2095,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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fprintf (file, "X");
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return;
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case 'A':
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case 'Q':
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/* Likewise, for BR -> BRA. */
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if (TARGET_LARGE)
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fprintf (file, "A");
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@ -2053,6 +2109,12 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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msp430_initial_elimination_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM)
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- 2);
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return;
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case 0:
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break;
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default:
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output_operand_lossage ("invalid operand prefix");
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return;
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}
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switch (GET_CODE (op))
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@ -87,7 +87,7 @@
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[(unspec_volatile [(match_operand 0 "register_operand" "r")
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(match_operand 1 "immediate_operand" "n")] UNS_PUSHM)]
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""
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"PUSHM%B0\t%1, %0"
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"PUSHM%b0\t%1, %0"
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)
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(define_insn "pop"
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@ -105,7 +105,7 @@
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)
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;; This is nasty. Operand0 is bogus. It is only there so that we can get a
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;; mode for the %B0 to work. We should use operand1 for this, but that does
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;; mode for the %b0 to work. We should use operand1 for this, but that does
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;; not have a mode.
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;;
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;; Operand1 is actually a register, but we cannot accept (REG...) because the
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@ -115,7 +115,7 @@
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;; because that is the only operator that will omit the # prefix to an
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;; integer value. Unfortunately it also inverts the integer value, so we
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;; have pre-invert it when generating this insn. (We could of course add a
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;; new operator, eg %D, just for this pattern...)
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;; new operator, eg %J, just for this pattern...)
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;;
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;; The pushm pattern does not have this problem because of all of the
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;; frame info cruft attached to it, so cprop_hardreg leaves it alone.
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@ -124,7 +124,7 @@
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(match_operand 1 "immediate_operand" "i")
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(match_operand 2 "immediate_operand" "i")] UNS_POPM)]
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""
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"POPM%B0\t%2, r%I1"
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"POPM%b0\t%2, r%I1"
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)
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;; The next two patterns are here to support a "feature" of how GCC implements
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@ -215,9 +215,9 @@
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(match_operand:PSI 1 "msp_general_operand" "riYa,r,rmi"))]
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""
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"@
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MOV%A0\t%1, %0
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MOV%A0\t%1, %0
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MOV%X0.%A0\t%1, %0")
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MOV%Q0\t%1, %0
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MOV%Q0\t%1, %0
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MOV%X0.%Q0\t%1, %0")
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; This pattern is identical to the truncsipsi2 pattern except
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; that it uses a SUBREG instead of a TRUNC. It is needed in
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@ -316,7 +316,7 @@
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; that are not single_set() very well.
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(define_insn "addhi3_cy"
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[(set (match_operand:HI 0 "msp_nonimmediate_operand" "=r,rm")
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[(set (match_operand:HI 0 "msp_nonimmediate_operand" "=r,rm")
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(plus:HI (match_operand:HI 1 "msp_nonimmediate_operand" "%0,0")
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(match_operand:HI 2 "msp_general_operand" "r,rm")))
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(set (reg:BI CARRY)
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@ -347,7 +347,7 @@
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; Version of addhi that adds the carry, for SImode adds.
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(define_insn "addchi4_cy"
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[(set (match_operand:HI 0 "msp_nonimmediate_operand" "=r,rm")
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[(set (match_operand:HI 0 "msp_nonimmediate_operand" "=r,rm")
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(plus:HI (plus:HI (match_operand:HI 1 "msp_nonimmediate_operand" "%0,0")
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(match_operand:HI 2 "msp_general_operand" "ri,rmi"))
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(zero_extend:HI (reg:BI CARRY))))
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@ -362,7 +362,7 @@
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; so that gcc knows when it can and can't optimize away the two
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; halves.
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(define_split
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[(set (match_operand:SI 0 "msp430_nonsubreg_operand")
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[(set (match_operand:SI 0 "msp430_nonsubreg_operand")
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(plus:SI (match_operand:SI 1 "nonimmediate_operand")
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(match_operand:SI 2 "general_operand")))
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]
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@ -452,8 +452,8 @@
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(match_operand 2 "msp430_inv_constgen_operator" "n,n")))]
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""
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"@
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BIC%x0%B0\t#%I2, %0
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BIC%X0%B0\t#%I2, %0"
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BIC%x0%b0\t#%I2, %0
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BIC%X0%b0\t#%I2, %0"
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)
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(define_insn "bic<mode>3"
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@ -462,8 +462,8 @@
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(match_operand:QHI 2 "msp_nonimmediate_operand" "0,0")))]
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""
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"@
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BIC%x0%B0\t%1, %0
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BIC%X0%B0\t%1, %0"
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BIC%x0%b0\t%1, %0
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BIC%X0%b0\t%1, %0"
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)
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(define_insn "and<mode>3"
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@ -472,42 +472,42 @@
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(match_operand:QHI 2 "msp_general_operand" "riYs,rmi")))]
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""
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"@
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AND%x0%B0\t%2, %0
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AND%X0%B0\t%2, %0"
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AND%x0%b0\t%2, %0
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AND%X0%b0\t%2, %0"
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)
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(define_insn "ior<mode>3"
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[(set (match_operand:QHI 0 "msp_nonimmediate_operand" "=rYs,rm")
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[(set (match_operand:QHI 0 "msp_nonimmediate_operand" "=rYs,rm")
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(ior:QHI (match_operand:QHI 1 "msp_nonimmediate_operand" "%0,0")
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(match_operand:QHI 2 "msp_general_operand" "riYs,rmi")))]
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""
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"@
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BIS%x0%B0\t%2, %0
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BIS%X0%B0\t%2, %0"
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BIS%x0%b0\t%2, %0
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BIS%X0%b0\t%2, %0"
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)
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(define_insn "xor<mode>3"
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[(set (match_operand:QHI 0 "msp_nonimmediate_operand" "=rYs,rm")
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[(set (match_operand:QHI 0 "msp_nonimmediate_operand" "=rYs,rm")
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(xor:QHI (match_operand:QHI 1 "msp_nonimmediate_operand" "%0,0")
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(match_operand:QHI 2 "msp_general_operand" "riYs,rmi")))]
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""
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"@
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XOR%x0%B0\t%2, %0
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XOR%X0%B0\t%2, %0"
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XOR%x0%b0\t%2, %0
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XOR%X0%b0\t%2, %0"
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)
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;; Macro : XOR #~0, %0
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(define_insn "one_cmpl<mode>2"
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[(set (match_operand:QHI 0 "msp_nonimmediate_operand" "=rYs,m")
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[(set (match_operand:QHI 0 "msp_nonimmediate_operand" "=rYs,m")
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(not:QHI (match_operand:QHI 1 "msp_nonimmediate_operand" "0,0")))]
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""
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"@
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INV%x0%B0\t%0
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INV%X0%B0\t%0"
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INV%x0%b0\t%0
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INV%X0%b0\t%0"
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)
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(define_insn "extendqihi2"
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[(set (match_operand:HI 0 "msp_nonimmediate_operand" "=rYs,m")
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[(set (match_operand:HI 0 "msp_nonimmediate_operand" "=rYs,m")
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(sign_extend:HI (match_operand:QI 1 "msp_nonimmediate_operand" "0,0")))]
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""
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"@
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@ -920,7 +920,7 @@
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(define_insn "epilogue_helper"
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[(unspec_volatile [(match_operand 0 "immediate_operand" "i")] UNS_EPILOGUE_HELPER)]
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""
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"BR%A0\t#__mspabi_func_epilog_%D0"
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"BR%Q0\t#__mspabi_func_epilog_%0"
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)
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@ -956,7 +956,7 @@
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[(call (mem:HI (match_operand 0 "general_operand" "rmi"))
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(match_operand 1 ""))]
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""
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"CALL%A0\t%0"
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"CALL%Q0\t%0"
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)
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(define_expand "call_value"
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@ -972,7 +972,7 @@
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(call (mem:HI (match_operand 1 "general_operand" "rmi"))
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(match_operand 2 "")))]
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""
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"CALL%A0\t%1"
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"CALL%Q0\t%1"
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)
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(define_insn "msp_return"
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@ -1010,7 +1010,7 @@
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[(set (pc)
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(label_ref (match_operand 0 "" "")))]
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""
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"BR%A0\t#%l0"
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"BR%Q0\t#%l0"
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)
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;; FIXME: GCC currently (8/feb/2013) cannot handle symbol_refs
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@ -1019,7 +1019,7 @@
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[(set (pc)
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(match_operand 0 "nonimmediate_operand" "rYl"))]
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""
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"BR%A0\t%0"
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"BR%Q0\t%0"
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)
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;;------------------------------------------------------------
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@ -1049,7 +1049,7 @@
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]
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""
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"@
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CMP%A0\t%2, %1 { J%0\t%l3
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CMP%Q0\t%2, %1 { J%0\t%l3
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CMPX.A\t%2, %1 { J%0\t%l3
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CMPX.A\t%2, %1 { J%0\t%l3"
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)
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@ -1095,7 +1095,7 @@
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]
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""
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"@
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CMP%A0\t%1, %2 { J%R0\t%l3
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CMP%Q0\t%1, %2 { J%R0\t%l3
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CMPX.A\t%1, %2 { J%R0\t%l3
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CMPX.A\t%1, %2 { J%R0\t%l3"
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)
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@ -1141,8 +1141,8 @@
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]
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""
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"@
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BIT%x0%B0\t%1, %0 { JNE\t%l2
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BIT%X0%B0\t%1, %0 { JNE\t%l2"
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BIT%x0%b0\t%1, %0 { JNE\t%l2
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BIT%X0%b0\t%1, %0 { JNE\t%l2"
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)
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(define_insn "*bitbranch<mode>4"
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|
@ -1155,7 +1155,7 @@
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(clobber (reg:BI CARRY))
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]
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""
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"BIT%x0%X0%B0\t%1, %0 { JEQ\t%l2"
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"BIT%x0%X0%b0\t%1, %0 { JEQ\t%l2"
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)
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(define_insn "*bitbranch<mode>4"
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|
@ -1168,7 +1168,7 @@
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(clobber (reg:BI CARRY))
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]
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""
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"BIT%X0%B0\t%1, %0 { JNE\t%l2"
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"BIT%X0%b0\t%1, %0 { JNE\t%l2"
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)
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(define_insn "*bitbranch<mode>4"
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|
@ -1181,7 +1181,7 @@
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(clobber (reg:BI CARRY))
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]
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""
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"BIT%X0%B0\t%1, %0 { JEQ\t%l2"
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"BIT%X0%b0\t%1, %0 { JEQ\t%l2"
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)
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;;------------------------------------------------------------
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@ -1199,8 +1199,8 @@
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]
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""
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"@
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BIT%x0%B0\t%p1, %0 { JNE\t%l2
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BIT%X0%B0\t%p1, %0 { JNE\t%l2"
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BIT%x0%b0\t%p1, %0 { JNE\t%l2
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BIT%X0%b0\t%p1, %0 { JNE\t%l2"
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)
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(define_insn "*bitbranch<mode>4_z"
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@ -1214,7 +1214,7 @@
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(clobber (reg:BI CARRY))
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]
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""
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"BIT%x0%X0%B0\t%p1, %0 { JEQ\t%l2"
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"BIT%x0%X0%b0\t%p1, %0 { JEQ\t%l2"
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)
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(define_insn "*bitbranch<mode>4_z"
|
||||
|
|
@ -1228,7 +1228,7 @@
|
|||
(clobber (reg:BI CARRY))
|
||||
]
|
||||
""
|
||||
"BIT%X0%B0\t%p1, %0 { JNE\t%l2"
|
||||
"BIT%X0%b0\t%p1, %0 { JNE\t%l2"
|
||||
)
|
||||
|
||||
(define_insn "*bitbranch<mode>4_z"
|
||||
|
|
@ -1242,7 +1242,7 @@
|
|||
(clobber (reg:BI CARRY))
|
||||
]
|
||||
""
|
||||
"BIT%X0%B0\t%p1, %0 { JEQ\t%l2"
|
||||
"BIT%X0%b0\t%p1, %0 { JEQ\t%l2"
|
||||
)
|
||||
|
||||
;;------------------------------------------------------------
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue