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aarch64: PR target/102252 Invalid addressing mode for SVE load predicate

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In the testcase we generate invalid assembly for an SVE load predicate instruction.
The RTL for the insn is:
(insn 9 8 10 (set (reg:VNx16BI 68 p0)
        (mem:VNx16BI (plus:DI (mult:DI (reg:DI 1 x1 [93])
                    (const_int 8 [0x8]))
                (reg/f:DI 0 x0 [92])) [2 work_3(D)->array[offset_4(D)]+0 S8 A16]))

That addressing mode is not valid for the instruction [1] as it only accepts the addressing mode:
[<Xn|SP>{, #<imm>, MUL VL}]

This patch rejects the register index form for SVE predicate modes.

Bootstrapped and tested on aarch64-none-linux-gnu.

[1] https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions/LDR--predicate---Load-predicate-register-

gcc/ChangeLog:

	PR target/102252
	* config/aarch64/aarch64.c (aarch64_classify_address): Don't allow
	register index for SVE predicate modes.

gcc/testsuite/ChangeLog:

	PR target/102252
	* g++.target/aarch64/sve/pr102252.C: New test.
This commit is contained in:
Kyrylo Tkachov 2021-09-13 15:40:28 +01:00
parent c7a669af0a
commit 512b383534
2 changed files with 42 additions and 4 deletions
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9
gcc/config/aarch64/aarch64.c
View file

@ -9770,7 +9770,6 @@ aarch64_classify_address (struct aarch64_address_info *info,
|| mode == TImode
|| mode == TFmode
|| (BYTES_BIG_ENDIAN && advsimd_struct_p));
/* If we are dealing with ADDR_QUERY_LDP_STP_N that means the incoming mode
corresponds to the actual size of the memory being loaded/stored and the
mode of the corresponding addressing mode is half of that. */
@ -9779,12 +9778,14 @@ aarch64_classify_address (struct aarch64_address_info *info,
mode = DFmode;
bool allow_reg_index_p = (!load_store_pair_p
&& (known_lt (GET_MODE_SIZE (mode), 16)
&& ((vec_flags == 0
&& known_lt (GET_MODE_SIZE (mode), 16))
|| vec_flags == VEC_ADVSIMD
|| vec_flags & VEC_SVE_DATA));
/* For SVE, only accept [Rn], [Rn, Rm, LSL #shift] and
[Rn, #offset, MUL VL]. */
/* For SVE, only accept [Rn], [Rn, #offset, MUL VL] and [Rn, Rm, LSL #shift].
The latter is not valid for SVE predicates, and that's rejected through
allow_reg_index_p above. */
if ((vec_flags & (VEC_SVE_DATA | VEC_SVE_PRED)) != 0
&& (code != REG && code != PLUS))
return false;

37
gcc/testsuite/g++.target/aarch64/sve/pr102252.C Normal file
View file

@ -0,0 +1,37 @@
/* PR target/102252. */
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
/* { dg-options "-march=armv8.2-a+sve -msve-vector-bits=512" } */
/* We used to generate invalid assembly for SVE predicate loads. */
#include <arm_sve.h>
class SimdBool
{
private:
typedef svbool_t simdInternalType_ __attribute__((arm_sve_vector_bits(512)));
public:
SimdBool() {}
simdInternalType_ simdInternal_;
};
static svfloat32_t selectByMask(svfloat32_t a, SimdBool m) {
return svsel_f32(m.simdInternal_, a, svdup_f32(0.0));
}
struct s {
SimdBool array[1];
};
void foo(struct s* const work, int offset)
{
svfloat32_t tz_S0;
tz_S0 = selectByMask(tz_S0, work->array[offset]);
}