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IBM Z: Remove redundant V_HW_64 mode iterator.

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gcc/ChangeLog:

	* config/s390/vector.md (V_HW_64): Remove mode iterator.
	(*vec_load_pair<mode>): Use V_HW_2 instead of V_HW_64.
	* config/s390/vx-builtins.md
	(vec_scatter_element<V_HW_2:mode>_SI): Use V_HW_2 instead of
	V_HW_64.
This commit is contained in:
Andreas Krebbel 2021-08-04 18:40:10 +02:00
parent 0aa7091bef
commit 4e34925ef1
2 changed files with 10 additions and 11 deletions
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7
gcc/config/s390/vector.md
View file

@ -36,7 +36,6 @@
(define_mode_iterator V_HW2 [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")
(V1TF "TARGET_VXE") (TF "TARGET_VXE")])
(define_mode_iterator V_HW_64 [V2DI V2DF])
(define_mode_iterator VT_HW_HSDT [V8HI V4SI V4SF V2DI V2DF V1TI V1TF TI TF])
(define_mode_iterator V_HW_HSD [V8HI V4SI (V4SF "TARGET_VXE") V2DI V2DF])
@ -1972,9 +1971,9 @@
})
(define_insn "*vec_load_pair<mode>"
[(set (match_operand:V_HW_64 0 "register_operand" "=v,v")
(vec_concat:V_HW_64 (match_operand:<non_vec> 1 "register_operand" "d,v")
(match_operand:<non_vec> 2 "register_operand" "d,v")))]
[(set (match_operand:V_HW_2 0 "register_operand" "=v,v")
(vec_concat:V_HW_2 (match_operand:<non_vec> 1 "register_operand" "d,v")
(match_operand:<non_vec> 2 "register_operand" "d,v")))]
"TARGET_VX"
"@
vlvgp\t%v0,%1,%2

14
gcc/config/s390/vx-builtins.md
View file

@ -452,17 +452,17 @@
; A 31 bit target address is generated from 64 bit elements
; vsceg
(define_insn "vec_scatter_element<V_HW_64:mode>_SI"
(define_insn "vec_scatter_element<V_HW_2:mode>_SI"
[(set (mem:<non_vec>
(plus:SI (subreg:SI
(unspec:<non_vec_int> [(match_operand:V_HW_64 1 "register_operand" "v")
(match_operand:QI 3 "const_mask_operand" "C")]
(unspec:<non_vec_int> [(match_operand:V_HW_2 1 "register_operand" "v")
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_EXTRACT) 4)
(match_operand:SI 2 "address_operand" "ZQ")))
(unspec:<non_vec> [(match_operand:V_HW_64 0 "register_operand" "v")
(match_operand:SI 2 "address_operand" "ZQ")))
(unspec:<non_vec> [(match_operand:V_HW_2 0 "register_operand" "v")
(match_dup 3)] UNSPEC_VEC_EXTRACT))]
"TARGET_VX && !TARGET_64BIT && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_64:MODE>mode)"
"vsce<V_HW_64:bhfgq>\t%v0,%O2(%v1,%R2),%3"
"TARGET_VX && !TARGET_64BIT && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_2:MODE>mode)"
"vsce<V_HW_2:bhfgq>\t%v0,%O2(%v1,%R2),%3"
[(set_attr "op_type" "VRV")])
; Element size and target address size is the same