* config/i386/i386.md: Move some more patterns around.
From-SVN: r242850
This commit is contained in:
Uros Bizjak
parent
3f156a6ce0
commit
4dec376c23
1 changed files with 106 additions and 106 deletions
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@ -8217,6 +8217,18 @@
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(const_string "*")))
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(set_attr "mode" "SI,DI,DI,SI,DI")])
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;; Turn *anddi_1 into *andsi_1_zext if possible.
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(and:DI (subreg:DI (match_operand:SI 1 "register_operand") 0)
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(match_operand:DI 2 "x86_64_zext_immediate_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT"
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[(parallel [(set (match_dup 0)
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(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[2] = gen_lowpart (SImode, operands[2]);")
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;; See comment for addsi_1_zext why we do use nonimmediate_operand
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(define_insn "*andsi_1_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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@ -8338,69 +8350,6 @@
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[(set_attr "type" "alu1")
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(set_attr "mode" "QI")])
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(define_insn "kandn<mode>"
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[(set (match_operand:SWI12 0 "register_operand" "=r,&r,!k")
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(and:SWI12
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(not:SWI12
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(match_operand:SWI12 1 "register_operand" "r,0,k"))
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(match_operand:SWI12 2 "register_operand" "r,r,k")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_AVX512F"
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{
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switch (which_alternative)
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{
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case 0:
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return "andn\t{%k2, %k1, %k0|%k0, %k1, %k2}";
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case 1:
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return "#";
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case 2:
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if (get_attr_mode (insn) == MODE_HI)
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return "kandnw\t{%2, %1, %0|%0, %1, %2}";
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else
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return "kandn<mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "isa" "bmi,*,avx512f")
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(set_attr "type" "bitmanip,*,msklog")
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(set_attr "prefix" "*,*,vex")
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(set_attr "btver2_decode" "direct,*,*")
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(set (attr "mode")
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(cond [(and (eq_attr "alternative" "2")
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(and (match_test "<MODE>mode == QImode")
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(not (match_test "TARGET_AVX512DQ"))))
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(const_string "HI")
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]
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(const_string "<MODE>")))])
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(define_split
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[(set (match_operand:SWI12 0 "general_reg_operand")
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(and:SWI12
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(not:SWI12
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(match_dup 0))
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(match_operand:SWI12 1 "general_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_AVX512F && !TARGET_BMI && reload_completed"
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[(set (match_dup 0)
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(not:SWI12 (match_dup 0)))
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(parallel [(set (match_dup 0)
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(and:SWI12 (match_dup 0)
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(match_dup 1)))
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(clobber (reg:CC FLAGS_REG))])])
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;; Turn *anddi_1 into *andsi_1_zext if possible.
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(and:DI (subreg:DI (match_operand:SI 1 "register_operand") 0)
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(match_operand:DI 2 "x86_64_zext_immediate_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT"
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[(parallel [(set (match_dup 0)
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(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[2] = gen_lowpart (SImode, operands[2]);")
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(define_split
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[(set (match_operand:SWI248 0 "register_operand")
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(and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")
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@ -8716,6 +8665,100 @@
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operands[1] = gen_lowpart (QImode, operands[1]);
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operands[2] = gen_lowpart (QImode, operands[2]);
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})
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(define_insn "kandn<mode>"
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[(set (match_operand:SWI12 0 "register_operand" "=r,&r,!k")
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(and:SWI12
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(not:SWI12
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(match_operand:SWI12 1 "register_operand" "r,0,k"))
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(match_operand:SWI12 2 "register_operand" "r,r,k")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_AVX512F"
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{
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switch (which_alternative)
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{
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case 0:
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return "andn\t{%k2, %k1, %k0|%k0, %k1, %k2}";
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case 1:
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return "#";
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case 2:
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if (get_attr_mode (insn) == MODE_HI)
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return "kandnw\t{%2, %1, %0|%0, %1, %2}";
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else
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return "kandn<mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "isa" "bmi,*,avx512f")
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(set_attr "type" "bitmanip,*,msklog")
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(set_attr "prefix" "*,*,vex")
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(set_attr "btver2_decode" "direct,*,*")
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(set (attr "mode")
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(cond [(and (eq_attr "alternative" "2")
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(and (match_test "<MODE>mode == QImode")
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(not (match_test "TARGET_AVX512DQ"))))
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(const_string "HI")
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]
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(const_string "<MODE>")))])
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(define_split
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[(set (match_operand:SWI12 0 "general_reg_operand")
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(and:SWI12
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(not:SWI12
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(match_dup 0))
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(match_operand:SWI12 1 "general_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_AVX512F && !TARGET_BMI && reload_completed"
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[(set (match_dup 0)
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(not:SWI12 (match_dup 0)))
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(parallel [(set (match_dup 0)
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(and:SWI12 (match_dup 0)
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(match_dup 1)))
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(clobber (reg:CC FLAGS_REG))])])
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(define_insn_and_split "*andndi3_doubleword"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(and:DI
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(not:DI (match_operand:DI 1 "register_operand" "r"))
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(match_operand:DI 2 "nonimmediate_operand" "rm")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE"
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"#"
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"&& reload_completed"
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[(parallel [(set (match_dup 0)
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(and:SI (not:SI (match_dup 1)) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])
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(parallel [(set (match_dup 3)
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(and:SI (not:SI (match_dup 4)) (match_dup 5)))
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(clobber (reg:CC FLAGS_REG))])]
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"split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);")
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(define_insn "*bmi_andn_<mode>"
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[(set (match_operand:SWI48 0 "register_operand" "=r,r")
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(and:SWI48
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(not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r"))
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(match_operand:SWI48 2 "nonimmediate_operand" "r,m")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI"
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"andn\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "bitmanip")
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(set_attr "btver2_decode" "direct, double")
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(set_attr "mode" "<MODE>")])
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(define_insn "*bmi_andn_<mode>_ccno"
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[(set (reg FLAGS_REG)
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(compare
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(and:SWI48
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(not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r"))
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(match_operand:SWI48 2 "nonimmediate_operand" "r,m"))
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(const_int 0)))
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(clobber (match_scratch:SWI48 0 "=r,r"))]
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"TARGET_BMI && ix86_match_ccmode (insn, CCNOmode)"
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"andn\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "bitmanip")
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(set_attr "btver2_decode" "direct, double")
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(set_attr "mode" "<MODE>")])
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;; Logical inclusive and exclusive OR instructions
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@ -13156,49 +13199,6 @@
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;; BMI instructions.
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(define_insn_and_split "*andndi3_doubleword"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(and:DI
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(not:DI (match_operand:DI 1 "register_operand" "r"))
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(match_operand:DI 2 "nonimmediate_operand" "rm")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE"
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"#"
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"&& reload_completed"
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[(parallel [(set (match_dup 0)
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(and:SI (not:SI (match_dup 1)) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])
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(parallel [(set (match_dup 3)
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(and:SI (not:SI (match_dup 4)) (match_dup 5)))
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(clobber (reg:CC FLAGS_REG))])]
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"split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);")
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(define_insn "*bmi_andn_<mode>"
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[(set (match_operand:SWI48 0 "register_operand" "=r,r")
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(and:SWI48
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(not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r"))
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(match_operand:SWI48 2 "nonimmediate_operand" "r,m")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI"
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"andn\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "bitmanip")
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(set_attr "btver2_decode" "direct, double")
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(set_attr "mode" "<MODE>")])
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(define_insn "*bmi_andn_<mode>_ccno"
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[(set (reg FLAGS_REG)
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(compare
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(and:SWI48
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(not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r"))
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(match_operand:SWI48 2 "nonimmediate_operand" "r,m"))
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(const_int 0)))
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(clobber (match_scratch:SWI48 0 "=r,r"))]
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"TARGET_BMI && ix86_match_ccmode (insn, CCNOmode)"
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"andn\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "bitmanip")
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(set_attr "btver2_decode" "direct, double")
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(set_attr "mode" "<MODE>")])
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(define_insn "bmi_bextr_<mode>"
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[(set (match_operand:SWI48 0 "register_operand" "=r,r")
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(unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "r,m")
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