RISC-V: Implement `riscv_emit_unary' helper
Add a `riscv_emit_unary' helper for unary operations, complementing `riscv_emit_binary'. gcc/ * config/riscv/riscv-protos.h (riscv_emit_unary): New prototype. * config/riscv/riscv.cc (riscv_emit_unary): New function.
This commit is contained in:
parent
6e32373214
commit
4daeedcbaf
2 changed files with 9 additions and 0 deletions
|
@ -134,6 +134,7 @@ riscv_zcmp_valid_stack_adj_bytes_p (HOST_WIDE_INT, int);
|
|||
extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0);
|
||||
extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
|
||||
extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
|
||||
extern rtx riscv_emit_unary (enum rtx_code code, rtx dest, rtx x);
|
||||
extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y);
|
||||
#endif
|
||||
extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx);
|
||||
|
|
|
@ -1732,6 +1732,14 @@ riscv_emit_set (rtx target, rtx src)
|
|||
return target;
|
||||
}
|
||||
|
||||
/* Emit an instruction of the form (set DEST (CODE X)). */
|
||||
|
||||
rtx
|
||||
riscv_emit_unary (enum rtx_code code, rtx dest, rtx x)
|
||||
{
|
||||
return riscv_emit_set (dest, gen_rtx_fmt_e (code, GET_MODE (dest), x));
|
||||
}
|
||||
|
||||
/* Emit an instruction of the form (set DEST (CODE X Y)). */
|
||||
|
||||
rtx
|
||||
|
|
Loading…
Add table
Reference in a new issue