FreeChainXenon/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

MIPS: Fix wrong MSA FP vector negation

Browse source 
We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
wrong because -0.0 is not 0 - 0.0.  This causes some Python tests to
fail when Python is built with MSA enabled.

Use the bnegi.df instructions to simply reverse the sign bit instead.

gcc/ChangeLog:

	* config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
	(neg<mode>2): Change the mode iterator from MSA to IMSA because
	in FP arithmetic we cannot use (0 - x) for -x.
	(neg<mode>2): New define_insn to implement FP vector negation,
	using a bnegi instruction to negate the sign bit.
This commit is contained in:
Xi Ruoyao 2024-02-03 03:35:07 +08:00
parent 42959acb84
commit 4d7fe3cf82
No known key found for this signature in database
GPG key ID: ACAAD20E19E710E3
1 changed files with 15 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
gcc/config/mips/mips-msa.md
View file

@ -231,6 +231,10 @@
(V4SI "uimm5")
(V2DI "uimm6")])
;; The index of sign bit in FP vector elements.
(define_mode_attr elmsgnbit [(V2DF "63") (V4DF "63")
(V4SF "31") (V8SF "31")])
(define_expand "vec_init<mode><unitmode>"
[(match_operand:MSA 0 "register_operand")
(match_operand:MSA 1 "")]
@ -597,9 +601,9 @@
})
(define_expand "neg<mode>2"
[(set (match_operand:MSA 0 "register_operand")
(minus:MSA (match_dup 2)
(match_operand:MSA 1 "register_operand")))]
[(set (match_operand:IMSA 0 "register_operand")
(minus:IMSA (match_dup 2)
(match_operand:IMSA 1 "register_operand")))]
"ISA_HAS_MSA"
{
rtx reg = gen_reg_rtx (<MODE>mode);
@ -607,6 +611,14 @@
operands[2] = reg;
})
(define_insn "neg<mode>2"
[(set (match_operand:FMSA 0 "register_operand" "=f")
(neg (match_operand:FMSA 1 "register_operand" "f")))]
"ISA_HAS_MSA"
"bnegi.<msafmt>\t%w0,%w1,<elmsgnbit>"
[(set_attr "type" "simd_bit")
(set_attr "mode" "<MODE>")])
(define_expand "msa_ldi<mode>"
[(match_operand:IMSA 0 "register_operand")
(match_operand 1 "const_imm10_operand")]