RISC-V/testsuite: Add branched cases for FP NE cond-move operations
Verify, for generic, Ventana and Zicond targets and the floating-point NE conditional-move operation, that if-conversion does *not* trigger at the respective sufficiently low `-mbranch-cost=' settings that make original branched code sequences cheaper than their branchless equivalents if-conversion would emit. gcc/testsuite/ * gcc.target/riscv/movdibfeq-ventana.c: New test. * gcc.target/riscv/movdibfeq-zicond.c: New test. * gcc.target/riscv/movdibfeq.c: New test. * gcc.target/riscv/movsibfeq-ventana.c: New test. * gcc.target/riscv/movsibfeq-zicond.c: New test. * gcc.target/riscv/movsibfeq.c: New test.
This commit is contained in:
Maciej W. Rozycki
parent
9a1a2e9857
commit
4c69b5fbb9
6 changed files with 176 additions and 0 deletions
30
gcc/testsuite/gcc.target/riscv/movdibfeq-ventana.c
Normal file
30
gcc/testsuite/gcc.target/riscv/movdibfeq-ventana.c
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@ -0,0 +1,30 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target rv64 } */
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/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
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/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
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typedef int __attribute__ ((mode (DI))) int_t;
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int_t
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movdifeq (double w, double x, int_t y, int_t z)
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{
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return w == x ? y : z;
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}
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/* Expect branched assembly like:
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feq.d a4,fa0,fa1
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mv a5,a0
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mv a0,a1
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beq a4,zero,.L2
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mv a0,a5
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.L2:
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*/
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/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
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/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
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/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
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/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
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/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
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/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
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/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
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30
gcc/testsuite/gcc.target/riscv/movdibfeq-zicond.c
Normal file
30
gcc/testsuite/gcc.target/riscv/movdibfeq-zicond.c
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@ -0,0 +1,30 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target rv64 } */
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/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
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/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
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typedef int __attribute__ ((mode (DI))) int_t;
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int_t
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movdifeq (double w, double x, int_t y, int_t z)
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{
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return w == x ? y : z;
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}
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/* Expect branched assembly like:
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feq.d a4,fa0,fa1
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mv a5,a0
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mv a0,a1
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beq a4,zero,.L2
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mv a0,a5
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.L2:
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*/
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/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
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/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
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/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
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/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
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/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
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/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
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/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
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28
gcc/testsuite/gcc.target/riscv/movdibfeq.c
Normal file
28
gcc/testsuite/gcc.target/riscv/movdibfeq.c
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@ -0,0 +1,28 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target rv64 } */
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/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
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/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
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typedef int __attribute__ ((mode (DI))) int_t;
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int_t
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movdifeq (double w, double x, int_t y, int_t z)
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{
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return w == x ? y : z;
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}
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/* Expect branched assembly like:
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feq.d a4,fa0,fa1
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mv a5,a0
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mv a0,a1
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beq a4,zero,.L2
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mv a0,a5
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.L2:
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*/
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/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
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/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
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/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
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/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
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/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
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30
gcc/testsuite/gcc.target/riscv/movsibfeq-ventana.c
Normal file
30
gcc/testsuite/gcc.target/riscv/movsibfeq-ventana.c
Normal file
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@ -0,0 +1,30 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target rv64 } */
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/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
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/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
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typedef int __attribute__ ((mode (SI))) int_t;
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int_t
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movsifeq (double w, double x, int_t y, int_t z)
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{
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return w == x ? y : z;
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}
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/* Expect branched assembly like:
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feq.d a4,fa0,fa1
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mv a5,a0
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mv a0,a1
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beq a4,zero,.L2
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mv a0,a5
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.L2:
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*/
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/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
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/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
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/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
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/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
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/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
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/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
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/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
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30
gcc/testsuite/gcc.target/riscv/movsibfeq-zicond.c
Normal file
30
gcc/testsuite/gcc.target/riscv/movsibfeq-zicond.c
Normal file
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@ -0,0 +1,30 @@
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/* { dg-do compile } */
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/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
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/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
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/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
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typedef int __attribute__ ((mode (SI))) int_t;
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int_t
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movsifeq (double w, double x, int_t y, int_t z)
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{
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return w == x ? y : z;
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}
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/* Expect branched assembly like:
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feq.d a4,fa0,fa1
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mv a5,a0
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mv a0,a1
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beq a4,zero,.L2
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mv a0,a5
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.L2:
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*/
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/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
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/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
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/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
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/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
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/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
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/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
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/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
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28
gcc/testsuite/gcc.target/riscv/movsibfeq.c
Normal file
28
gcc/testsuite/gcc.target/riscv/movsibfeq.c
Normal file
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@ -0,0 +1,28 @@
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/* { dg-do compile } */
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/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
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/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
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/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
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typedef int __attribute__ ((mode (SI))) int_t;
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int_t
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movsifeq (double w, double x, int_t y, int_t z)
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{
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return w == x ? y : z;
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}
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/* Expect branched assembly like:
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feq.d a4,fa0,fa1
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mv a5,a0
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mv a0,a1
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beq a4,zero,.L2
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mv a0,a5
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.L2:
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*/
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/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
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/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
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/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
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/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
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/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
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