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scheduler improvements for BD architectures

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From-SVN: r204442
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Ganesh Gopalasubramanian 2013-11-06 05:38:09 +00:00 • committed by Ganesh Gopalasubramanian
parent 3118d595a6
commit 4a1db8e164
3 changed files with 29 additions and 11 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2013-11-06 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
* config/i386/bdver3.md : Added two additional decoder units
to support issue rate of 4 and remodeled vector unit.
* config/i386/i386.c (ix86_issue_rate): Issue rate for BD
architectures is set to 4.
* config/i386/i386.c (ia32_multipass_dfa_lookahead): DFA
lookahead is set to 4 for BD architectures.
2013-11-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_option_override_internal):

18
gcc/config/i386/bdver3.md
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@ -34,20 +34,22 @@
(define_cpu_unit "bdver3-decode0" "bdver3")
(define_cpu_unit "bdver3-decode1" "bdver3")
(define_cpu_unit "bdver3-decodev" "bdver3")
(define_cpu_unit "bdver3-decode2" "bdver3")
(define_cpu_unit "bdver3-decode3" "bdver3")
;; Double decoded instructions take two cycles whereas
;; direct instructions take one cycle.
;; Therefore four direct instructions can be decoded by
;; two decoders in two cycles.
;; Vectorpath instructions are single issue instructions.
;; So, we have separate unit for vector instructions.
(exclusion_set "bdver3-decodev" "bdver3-decode0,bdver3-decode1")
;; So, we engage all units vector instructions.
(define_reservation "bdver3-vector" "bdver3-decode0+bdver3-decode1+bdver3-decode2+bdver3-decode3")
;; Direct instructions can be issued to any of the four decoders
(define_reservation "bdver3-direct" "(bdver3-decode0|bdver3-decode1|bdver3-decode2|bdver3-decode3)")
(define_reservation "bdver3-vector" "bdver3-decodev")
(define_reservation "bdver3-direct" "(bdver3-decode0|bdver3-decode1)")
;; Double instructions take two cycles to decode.
(define_reservation "bdver3-double" "(bdver3-decode0|bdver3-decode1)*2")
(define_reservation "bdver3-double" "(bdver3-decode0,bdver3-decode0)|
(bdver3-decode1,bdver3-decode1)| (bdver3-decode2,bdver3-decode2)|
(bdver3-decode3,bdver3-decode3)")
(define_cpu_unit "bdver3-ieu0" "bdver3_ieu")
(define_cpu_unit "bdver3-ieu1" "bdver3_ieu")

13
gcc/config/i386/i386.c
View file

@ -24830,12 +24830,12 @@ ix86_issue_rate (void)
case PROCESSOR_K8:
case PROCESSOR_AMDFAM10:
case PROCESSOR_GENERIC:
case PROCESSOR_BDVER1:
case PROCESSOR_BDVER2:
case PROCESSOR_BDVER3:
case PROCESSOR_BTVER1:
return 3;
case PROCESSOR_BDVER1:
case PROCESSOR_BDVER2:
case PROCESSOR_BDVER3:
case PROCESSOR_CORE2:
case PROCESSOR_COREI7:
case PROCESSOR_COREI7_AVX:
@ -25212,6 +25212,13 @@ ia32_multipass_dfa_lookahead (void)
case PROCESSOR_K6:
return 1;
case PROCESSOR_BDVER1:
case PROCESSOR_BDVER2:
case PROCESSOR_BDVER3:
/* We use lookahead value 4 for BD both before and after reload
schedules. Plan is to have value 8 included for O3. */
return 4;
case PROCESSOR_CORE2:
case PROCESSOR_COREI7:
case PROCESSOR_COREI7_AVX: