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texi2pod.pl: Handle "\,".

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contrib:
	* texi2pod.pl: Handle "\,".

gcc:
	* gcc.1, cpp.1: Regenerate.

From-SVN: r39244
This commit is contained in:
Joseph Myers 2001-01-24 19:47:47 +00:00 • committed by Joseph Myers
parent c347e89206
commit 445c435a52
5 changed files with 125 additions and 10 deletions
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4
contrib/ChangeLog
View file

@ -1,3 +1,7 @@
2001-01-24 Joseph S. Myers <jsm28@cam.ac.uk>
* texi2pod.pl: Handle "\,".
2001-01-15 Joseph S. Myers <jsm28@cam.ac.uk>
* texi2pod.pl: Fix regular expression for @r to avoid exponential

1
contrib/texi2pod.pl
View file

@ -144,6 +144,7 @@ while(<STDIN>)
s/\@TeX\{\}/TeX/g;
s/\@pounds\{\}/\#/g;
s/\@minus(?:\{\})?/-/g;
s/\\,/,/g;
# Now the ones that have to be replaced by special escapes
# (which will be turned back into text by unmunge())

4
gcc/ChangeLog
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@ -1,3 +1,7 @@
2001-01-24 Joseph S. Myers <jsm28@cam.ac.uk>
* gcc.1, cpp.1: Regenerate.
2001-01-24 Alexandre Oliva <aoliva@redhat.com>
* calls.c (emit_library_call_value_1): Memory slot for

14
gcc/cpp.1
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@ -1,5 +1,5 @@
.\" Automatically generated by Pod::Man version 1.1
.\" Fri Jan 12 18:47:56 2001
.\" Wed Jan 24 19:43:25 2001
.\"
.\" Standard preamble:
.\" ======================================================================
@ -138,7 +138,7 @@
.\" ======================================================================
.\"
.IX Title "CPP 1"
.TH CPP 1 "gcc-2.97" "2001-01-12" "GNU"
.TH CPP 1 "gcc-2.97" "2001-01-24" "GNU"
.UC
.SH "NAME"
cpp \- The C Preprocessor
@ -509,13 +509,15 @@ Instead of outputting the result of preprocessing, output a rule
suitable for \f(CW\*(C`make\*(C'\fR describing the dependencies of the main source
file. The preprocessor outputs one \f(CW\*(C`make\*(C'\fR rule containing the
object file name for that source file, a colon, and the names of all the
included files. If there are many included files then the rule is split
into several lines using \fB\e\fR\-newline.
included files, including those coming from \fB\-include\fR or
\&\fB\-imacros\fR command line options. If there are many included files
then the rule is split into several lines using \fB\e\fR\-newline.
.Ip "\fB\-MM\fR" 4
.IX Item "-MM"
Like \fB\-M\fR, but mention only the files included with \fB#include
"\fR\fIfile\fR\fB"\fR. System header files included with \fB#include
<\fR\fIfile\fR\fB>\fR are omitted.
"\fR\fIfile\fR\fB"\fR or with \fB\-include\fR or \fB\-imacros\fR command line
options. System header files included with \fB#include <\fR\fIfile\fR\fB>\fR
are omitted.
.Ip "\fB\-MF\fR \fIfile\fR" 4
.IX Item "-MF file"
When used with \fB\-M\fR or \fB\-MM\fR, specifies a file to write the

112
gcc/gcc.1
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@ -1,5 +1,5 @@
.\" Automatically generated by Pod::Man version 1.1
.\" Fri Jan 12 20:37:33 2001
.\" Wed Jan 24 19:43:11 2001
.\"
.\" Standard preamble:
.\" ======================================================================
@ -138,7 +138,7 @@
.\" ======================================================================
.\"
.IX Title "GCC 1"
.TH GCC 1 "gcc-2.97" "2001-01-12" "GNU"
.TH GCC 1 "gcc-2.97" "2001-01-24" "GNU"
.UC
.SH "NAME"
gcc \- \s-1GNU\s0 project C and \*(C+ compiler
@ -280,7 +280,8 @@ in the following sections.
\&\-finline-functions \-finline-limit=\fR\fIn\fR \fB\-fkeep-inline-functions
\&\-fkeep-static-consts \-fmove-all-movables
\&\-fno-default-inline \-fno-defer-pop
\&\-fno-function-cse \-fno-inline \-fno-math-errno \-fno-peephole
\&\-fno-function-cse \-fno-guess-branch-probability
\&\-fno-inline \-fno-math-errno \-fno-peephole
\&\-fomit-frame-pointer \-foptimize-register-move
\&\-foptimize-sibling-calls \-freduce-all-givs
\&\-fregmove \-frename-registers
@ -578,11 +579,19 @@ in the following sections.
.Sp
\&\fIMCore Options\fR
.Sp
\&\fB\-mhardlit, \-mno-hardlit \-mdiv \-mno-div \-mrelax-immediates
\&\fB\-mhardlit \-mno-hardlit \-mdiv \-mno-div \-mrelax-immediates
\&\-mno-relax-immediates \-mwide-bitfields \-mno-wide-bitfields
\&\-m4byte-functions \-mno-4byte-functions \-mcallgraph-data
\&\-mno-callgraph-data \-mslow-bytes \-mno-slow-bytes \-mno-lsim
\&\-mlittle-endian \-mbig-endian \-m210 \-m340 \-mstack-increment\fR
.Sp
\&\fI\s-1IA-64\s0 Options\fR
.Sp
\&\fB\-mbig-endian \-mlittle-endian \-mgnu-as \-mgnu-ld \-mno-pic
\&\-mvolatile-asm-stop \-mb-step \-mregister-names \-mno-sdata
\&\-mconstant-gp \-mauto-pic \-minline-divide-min-latency
\&\-minline-divide-max-throughput \-mno-dwarf2\-asm
\&\-mfixed-range=\fR\fIregister range\fR
.Ip "\fICode Generation Options\fR" 4
.IX Item "Code Generation Options"
\&\fB\-fcall-saved-\fR\fIreg\fR \fB\-fcall-used-\fR\fIreg\fR
@ -2991,6 +3000,15 @@ Disable any machine-specific peephole optimizations.
After running a program compiled with \fB\-fprofile-arcs\fR, you can compile it a second time using
\&\fB\-fbranch-probabilities\fR, to improve optimizations based on
guessing the path a branch might take.
.Ip "\fB\-fno-guess-branch-probability\fR" 4
.IX Item "-fno-guess-branch-probability"
Sometimes gcc will opt to guess branch probabilities when none are
available from either profile directed feedback (\fB\-fprofile-arcs\fR)
or \fB_\|_builtin_expect\fR. In a hard real-time system, people don't
want different runs of the compiler to produce code that has different
behavior; minimizing non-determinism is of paramount import. This
switch allows users to reduce non-determinism, possibly at the expense
of inferior optimization.
.Ip "\fB\-fstrict-aliasing\fR" 4
.IX Item "-fstrict-aliasing"
Allows the compiler to assume the strictest aliasing rules applicable to
@ -7166,6 +7184,92 @@ Generate code for a little endian target.
.PD
Generate code for the 210 processor.
.PP
.I "\s-1IA-64\s0 Options"
.IX Subsection "IA-64 Options"
.PP
These are the \fB\-m\fR options defined for the Intel \s-1IA-64\s0 architecture.
.Ip "\fB\-mbig-endian\fR" 4
.IX Item "-mbig-endian"
Generate code for a big endian target. This is the default for \s-1HPUX\s0.
.Ip "\fB\-mlittle-endian\fR" 4
.IX Item "-mlittle-endian"
Generate code for a little endian target. This is the default for \s-1AIX5\s0
and Linux.
.Ip "\fB\-mgnu-as\fR" 4
.IX Item "-mgnu-as"
.PD 0
.Ip "\fB\-mno-gnu-as\fR" 4
.IX Item "-mno-gnu-as"
.PD
Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default.
.Ip "\fB\-mgnu-ld\fR" 4
.IX Item "-mgnu-ld"
.PD 0
.Ip "\fB\-mno-gnu-ld\fR" 4
.IX Item "-mno-gnu-ld"
.PD
Generate (or don't) code for the \s-1GNU\s0 linker. This is the default.
.Ip "\fB\-mno-pic\fR" 4
.IX Item "-mno-pic"
Generate code that does not use a global pointer register. The result
is not position independent code, and violates the \s-1IA-64\s0 \s-1ABI\s0.
.Ip "\fB\-mvolatile-asm-stop\fR" 4
.IX Item "-mvolatile-asm-stop"
.PD 0
.Ip "\fB\-mno-volatile-asm-stop\fR" 4
.IX Item "-mno-volatile-asm-stop"
.PD
Generate (or don't) a stop bit immediately before and after volatile asm
statements.
.Ip "\fB\-mb-step\fR" 4
.IX Item "-mb-step"
Generate code that works around Itanium B step errata.
.Ip "\fB\-mregister-names\fR" 4
.IX Item "-mregister-names"
.PD 0
.Ip "\fB\-mno-register-names\fR" 4
.IX Item "-mno-register-names"
.PD
Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for
the stacked registers. This may make assembler output more readable.
.Ip "\fB\-mno-sdata\fR" 4
.IX Item "-mno-sdata"
.PD 0
.Ip "\fB\-msdata\fR" 4
.IX Item "-msdata"
.PD
Disable (or enable) optimizations that use the small data section. This may
be useful for working around optimizer bugs.
.Ip "\fB\-mconstant-gp\fR" 4
.IX Item "-mconstant-gp"
Generate code that uses a single constant global pointer value. This is
useful when compiling kernel code.
.Ip "\fB\-mauto-pic\fR" 4
.IX Item "-mauto-pic"
Generate code that is self-relocatable. This implies \fB\-mconstant-gp\fR.
This is useful when compiling firmware code.
.Ip "\fB\-minline-divide-min-latency\fR" 4
.IX Item "-minline-divide-min-latency"
Generate code for inline divides using the minimum latency algorithm.
.Ip "\fB\-minline-divide-max-throughput\fR" 4
.IX Item "-minline-divide-max-throughput"
Generate code for inline divides using the maximum throughput algorithm.
.Ip "\fB\-mno-dwarf2\-asm\fR" 4
.IX Item "-mno-dwarf2-asm"
.PD 0
.Ip "\fB\-mdwarf2\-asm\fR" 4
.IX Item "-mdwarf2-asm"
.PD
Don't (or do) generate assembler code for the \s-1DWARF2\s0 line number debugging
info. This may be useful when not using the \s-1GNU\s0 assembler.
.Ip "\fB\-mfixed-range=\fR\fIregister range\fR" 4
.IX Item "-mfixed-range=register range"
Generate code treating the given register range as fixed registers.
A fixed register is one that the register allocator can not use. This is
useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
.PP
.I "D30V Options"
.IX Subsection "D30V Options"
.PP