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arm: Add Arm Cortex-M52 CPU documentation.

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Signed-off-by: Chung-Ju Wu <jasonwucj@gmail.com>

gcc/ChangeLog:

	* doc/invoke.texi (Arm Options): Document Cortex-M52 options.
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Chung-Ju Wu 2024-01-09 14:26:18 +08:00
parent 6e249a9ad9
commit 43c4f98211
1 changed files with 13 additions and 13 deletions
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gcc/doc/invoke.texi
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@ -23103,7 +23103,7 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
@samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-r52plus},
@samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
@samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1},
@samp{cortex-m35p}, @samp{cortex-m52}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1},
@samp{cortex-x1c}, @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
@samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale},
@ -23169,34 +23169,34 @@ The following extension options are common to the listed CPUs:
@table @samp
@item +nodsp
Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p},
@samp{cortex-m55} and @samp{cortex-m85}. Also disable the M-Profile Vector
Extension (MVE) integer and single precision floating-point instructions on
@samp{cortex-m55} and @samp{cortex-m85}.
@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
Also disable the M-Profile Vector Extension (MVE) integer and
single precision floating-point instructions on
@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
@item +nopacbti
Disable the Pointer Authentication and Branch Target Identification Extension
on @samp{cortex-m85}.
on @samp{cortex-m52} and @samp{cortex-m85}.
@item +nomve
Disable the M-Profile Vector Extension (MVE) integer and single precision
floating-point instructions on @samp{cortex-m55} and @samp{cortex-m85}.
floating-point instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
@item +nomve.fp
Disable the M-Profile Vector Extension (MVE) single precision floating-point
instructions on @samp{cortex-m55} and @samp{cortex-m85}.
instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
@item +cdecp0, +cdecp1, ... , +cdecp7
Enable the Custom Datapath Extension (CDE) on selected coprocessors according
to the numbers given in the options in the range 0 to 7 on @samp{cortex-m55}.
to the numbers given in the options in the range 0 to 7 on @samp{cortex-m52} and @samp{cortex-m55}.
@item +nofp
Disables the floating-point instructions on @samp{arm9e},
@samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
@samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s},
@samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p}
@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p},
@samp{cortex-m55} and @samp{cortex-m85}.
@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
Disables the floating-point and SIMD instructions on
@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
@samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
@ -23539,9 +23539,9 @@ Development Tools Engineering Specification", which can be found on
Mitigate against a potential security issue with the @code{VLLDM} instruction
in some M-profile devices when using CMSE (CVE-2021-365465). This option is
enabled by default when the option @option{-mcpu=} is used with
@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55}, @code{cortex-m85}
or @code{star-mc1}. The option @option{-mno-fix-cmse-cve-2021-35465} can be used
to disable the mitigation.
@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m52}, @code{cortex-m55},
@code{cortex-m85} or @code{star-mc1}. The option @option{-mno-fix-cmse-cve-2021-35465}
can be used to disable the mitigation.
@opindex mstack-protector-guard
@opindex mstack-protector-guard-offset