Remove gen_cell_microcode, warn_cell_microcode
-mno-gen-cell-microcode is a pain to handle correctly: it causes different code generation for some very basic patterns, even patterns specific to that option. It also requires marking up many patterns, which is a pain when adding new patterns or modifying existing ones (first non-trivial step is finding the Cell BE manual!) -mwarn-cell-microcode is very expensive, even more so after my recent fix for PR43763; and it used to ICE for seven years before that fix. This patch removes both these command line options (it leaves the positive form of -mgen-cell-microcode, doing nothing, for compatibility). Where cc_reg_not_micro_cr0_operand was used, we now get the regular cc_reg_not_cr0_operand. One testcase used -mgen-cell-microcode and one its negation; both are adjusted. * config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): Delete. (lwa_operand): Delete rs6000_gen_cell_microcode test. * config/rs6000/rs6000.c (rs6000_option_override_internal): Delete rs6000_gen_cell_microcode code. (rs6000_final_prescan_insn): Delete. (rs6000_opt_vars): Delete the "gen-cell-microcode" and "warn-cell-microcode" entries. * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Delete. * config/rs6000/rs6000.md: Delete rs6000_gen_cell_microcode tests throughout. Change cc_reg_not_micro_cr0_operand to cc_reg_not_cr0_operand throughout. (*extendhi<mode>2_noload): Delete. * config/rs6000/rs6000.opt (mgen-cell-microcode): Replace by stub. (mwarn-cell-microcode): Delete. * doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mgen-cell-microcode and -mwarn-cell-microcode. gcc/testsuite/ * gcc.target/powerpc/shift-dot.c: Delete -mgen-cell-microcode from dg-options. * gfortran.dg/pr80107.f: Delete testcase. From-SVN: r248695
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
98c28dd4ba
commit
3f8efe25d6
10 changed files with 79 additions and 170 deletions
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@ -1,3 +1,22 @@
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2017-05-30 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): Delete.
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(lwa_operand): Delete rs6000_gen_cell_microcode test.
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* config/rs6000/rs6000.c (rs6000_option_override_internal): Delete
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rs6000_gen_cell_microcode code.
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(rs6000_final_prescan_insn): Delete.
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(rs6000_opt_vars): Delete the "gen-cell-microcode" and
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"warn-cell-microcode" entries.
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* config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Delete.
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* config/rs6000/rs6000.md: Delete rs6000_gen_cell_microcode tests
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throughout. Change cc_reg_not_micro_cr0_operand to
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cc_reg_not_cr0_operand throughout.
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(*extendhi<mode>2_noload): Delete.
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* config/rs6000/rs6000.opt (mgen-cell-microcode): Replace by stub.
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(mwarn-cell-microcode): Delete.
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* doc/invoke.texi (RS/6000 and PowerPC Options): Delete
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-mgen-cell-microcode and -mwarn-cell-microcode.
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2017-05-30 Uros Bizjak <ubizjak@gmail.com>
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PR target/80833
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@ -530,25 +530,6 @@
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return CR_REGNO_NOT_CR0_P (REGNO (op));
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})
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;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
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(define_predicate "cc_reg_not_micro_cr0_operand"
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(match_operand 0 "register_operand")
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{
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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if (!REG_P (op))
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return 0;
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if (REGNO (op) > LAST_VIRTUAL_REGISTER)
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return 1;
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if (rs6000_gen_cell_microcode)
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return CR_REGNO_NOT_CR0_P (REGNO (op));
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else
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return CR_REGNO_P (REGNO (op));
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})
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;; Return 1 if op is a constant integer valid for D field
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;; or non-special register register.
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(define_predicate "reg_or_short_operand"
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@ -1069,8 +1050,6 @@
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return true;
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if (!memory_operand (inner, mode))
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return false;
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if (!rs6000_gen_cell_microcode)
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return false;
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addr = XEXP (inner, 0);
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if (GET_CODE (addr) == PRE_INC
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@ -4260,16 +4260,9 @@ rs6000_option_override_internal (bool global_init_p)
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error ("SPE not supported in this target");
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}
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/* Disable Cell microcode if we are optimizing for the Cell
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and not optimizing for size. */
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if (rs6000_gen_cell_microcode == -1)
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rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
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&& !optimize_size);
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/* If we are optimizing big endian systems for space and it's OK to
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use instructions that would be microcoded on the Cell, use the
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load/store multiple and string instructions. */
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if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
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/* If we are optimizing big endian systems for space, use the load/store
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multiple and string instructions. */
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if (BYTES_BIG_ENDIAN && optimize_size)
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rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
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| OPTION_MASK_STRING);
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@ -39295,38 +39288,6 @@ rs6000_stack_protect_fail (void)
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: default_external_stack_protect_fail ();
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}
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void
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rs6000_final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
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int num_operands ATTRIBUTE_UNUSED)
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{
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if (rs6000_warn_cell_microcode)
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{
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const char *temp;
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int insn_code_number = recog_memoized (insn);
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location_t location = INSN_LOCATION (insn);
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/* Punt on insns we cannot recognize. */
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if (insn_code_number < 0)
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return;
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/* get_insn_template can modify recog_data, so save and restore it. */
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struct recog_data_d recog_data_save = recog_data;
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for (int i = 0; i < recog_data.n_operands; i++)
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recog_data.operand[i] = copy_rtx (recog_data.operand[i]);
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temp = get_insn_template (insn_code_number, insn);
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recog_data = recog_data_save;
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if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
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warning_at (location, OPT_mwarn_cell_microcode,
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"emitting microcode insn %s\t[%s] #%d",
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temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
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else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
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warning_at (location, OPT_mwarn_cell_microcode,
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"emitting conditional microcode insn %s\t[%s] #%d",
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temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
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}
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}
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/* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
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#if TARGET_ELF
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@ -39499,12 +39460,6 @@ static struct rs6000_opt_var const rs6000_opt_vars[] =
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{ "sched-epilog",
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offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
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offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
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{ "gen-cell-microcode",
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offsetof (struct gcc_options, x_rs6000_gen_cell_microcode),
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offsetof (struct cl_target_option, x_rs6000_gen_cell_microcode), },
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{ "warn-cell-microcode",
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offsetof (struct gcc_options, x_rs6000_warn_cell_microcode),
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offsetof (struct cl_target_option, x_rs6000_warn_cell_microcode), },
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};
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/* Inner function to handle attribute((target("..."))) and #pragma GCC target
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@ -2157,12 +2157,6 @@ do { \
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/* #define LEGITIMATE_PIC_OPERAND_P (X) */
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/* Define this if some processing needs to be done immediately before
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emitting code for an insn. */
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#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
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rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
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/* Specify the machine mode that this machine uses
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for the index in the tablejump instruction. */
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#define CASE_VECTOR_MODE SImode
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@ -726,7 +726,7 @@
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(compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:EXTQI 0 "=r,r"))]
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"rs6000_gen_cell_microcode"
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""
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"@
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andi. %0,%1,0xff
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#"
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@ -747,7 +747,7 @@
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(const_int 0)))
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(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
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(zero_extend:EXTQI (match_dup 1)))]
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"rs6000_gen_cell_microcode"
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""
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"@
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andi. %0,%1,0xff
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#"
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@ -779,7 +779,7 @@
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(compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:EXTHI 0 "=r,r"))]
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"rs6000_gen_cell_microcode"
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""
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"@
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andi. %0,%1,0xffff
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#"
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@ -800,7 +800,7 @@
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(const_int 0)))
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(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
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(zero_extend:EXTHI (match_dup 1)))]
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"rs6000_gen_cell_microcode"
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""
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"@
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andi. %0,%1,0xffff
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#"
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@ -835,7 +835,7 @@
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(compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:EXTSI 0 "=r,r"))]
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"rs6000_gen_cell_microcode"
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""
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"@
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rldicl. %0,%1,0,32
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#"
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@ -856,7 +856,7 @@
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(const_int 0)))
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(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
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(zero_extend:EXTSI (match_dup 1)))]
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"rs6000_gen_cell_microcode"
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""
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"@
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rldicl. %0,%1,0,32
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#"
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@ -886,7 +886,7 @@
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(compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:EXTQI 0 "=r,r"))]
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"rs6000_gen_cell_microcode"
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""
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"@
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extsb. %0,%1
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#"
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@ -907,7 +907,7 @@
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(const_int 0)))
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(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
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(sign_extend:EXTQI (match_dup 1)))]
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"rs6000_gen_cell_microcode"
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""
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"@
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extsb. %0,%1
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#"
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@ -932,7 +932,7 @@
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(define_insn "*extendhi<mode>2"
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[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*wK,?*wK")
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(sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wK")))]
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"rs6000_gen_cell_microcode || TARGET_VSX_SMALL_INTEGER"
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""
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"@
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lha%U1%X1 %0,%1
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extsh %0,%1
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@ -955,19 +955,12 @@
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operands[2] = gen_rtx_REG (HImode, REGNO (operands[1]));
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})
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(define_insn "*extendhi<mode>2_noload"
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[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
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(sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
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"!rs6000_gen_cell_microcode"
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"extsh %0,%1"
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[(set_attr "type" "exts")])
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(define_insn_and_split "*extendhi<mode>2_dot"
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[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
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(compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:EXTHI 0 "=r,r"))]
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"rs6000_gen_cell_microcode"
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""
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"@
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extsh. %0,%1
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#"
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@ -988,7 +981,7 @@
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(const_int 0)))
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(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
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(sign_extend:EXTHI (match_dup 1)))]
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"rs6000_gen_cell_microcode"
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""
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"@
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extsh. %0,%1
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#"
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@ -1052,7 +1045,7 @@
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(compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:EXTSI 0 "=r,r"))]
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"rs6000_gen_cell_microcode"
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""
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"@
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extsw. %0,%1
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#"
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@ -1073,7 +1066,7 @@
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(const_int 0)))
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(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
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(sign_extend:EXTSI (match_dup 1)))]
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"rs6000_gen_cell_microcode"
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""
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"@
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extsw. %0,%1
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#"
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@ -1941,7 +1934,7 @@
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(compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"<MODE>mode == Pmode"
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"@
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not. %0,%1
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#"
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@ -1962,7 +1955,7 @@
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(not:GPR (match_dup 1)))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"<MODE>mode == Pmode"
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"@
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not. %0,%1
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#"
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@ -2849,7 +2842,7 @@
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(match_operand:GPR 2 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"<MODE>mode == Pmode"
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"@
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mull<wd>. %0,%1,%2
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#"
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@ -2874,7 +2867,7 @@
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(mult:GPR (match_dup 1)
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(match_dup 2)))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"<MODE>mode == Pmode"
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"@
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mull<wd>. %0,%1,%2
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#"
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@ -3220,8 +3213,7 @@
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DONE;
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}
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if (logical_const_operand (operands[2], <MODE>mode)
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&& rs6000_gen_cell_microcode)
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if (logical_const_operand (operands[2], <MODE>mode))
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{
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emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
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DONE;
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@ -3243,8 +3235,7 @@
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(and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
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(match_operand:GPR 2 "logical_const_operand" "n")))
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(clobber (match_scratch:CC 3 "=x"))]
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"rs6000_gen_cell_microcode
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&& !rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
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"!rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
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"andi%e2. %0,%1,%u2"
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[(set_attr "type" "logical")
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(set_attr "dot" "yes")])
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@ -3257,7 +3248,6 @@
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(clobber (match_scratch:GPR 0 "=r,r"))
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(clobber (match_scratch:CC 4 "=X,x"))]
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"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
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&& rs6000_gen_cell_microcode
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&& !rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
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"@
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andi%e2. %0,%1,%u2
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@ -3285,7 +3275,6 @@
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(match_dup 2)))
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(clobber (match_scratch:CC 4 "=X,x"))]
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"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
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&& rs6000_gen_cell_microcode
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&& !rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
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"@
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andi%e2. %0,%1,%u2
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@ -3310,7 +3299,6 @@
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
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&& rs6000_gen_cell_microcode
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&& rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
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"@
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andi%e2. %0,%1,%u2
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@ -3336,7 +3324,6 @@
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(and:GPR (match_dup 1)
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(match_dup 2)))]
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"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
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&& rs6000_gen_cell_microcode
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&& rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
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"@
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andi%e2. %0,%1,%u2
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|
@ -3366,8 +3353,7 @@
|
|||
<< INTVAL (operands[4])),
|
||||
DImode)
|
||||
&& (<MODE>mode == Pmode
|
||||
|| (UINTVAL (operands[2]) << INTVAL (operands[4])) <= 0x7fffffff)
|
||||
&& rs6000_gen_cell_microcode"
|
||||
|| (UINTVAL (operands[2]) << INTVAL (operands[4])) <= 0x7fffffff)"
|
||||
{
|
||||
operands[2] = GEN_INT (UINTVAL (operands[2]) << INTVAL (operands[4]));
|
||||
return "andi%e2. %0,%1,%u2";
|
||||
|
|
@ -3393,7 +3379,6 @@
|
|||
(const_int 0)))
|
||||
(clobber (match_scratch:GPR 0 "=r,r"))]
|
||||
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
|
||||
&& rs6000_gen_cell_microcode
|
||||
&& !logical_const_operand (operands[2], <MODE>mode)
|
||||
&& rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
|
||||
{
|
||||
|
|
@ -3423,7 +3408,6 @@
|
|||
(and:GPR (match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
|
||||
&& rs6000_gen_cell_microcode
|
||||
&& !logical_const_operand (operands[2], <MODE>mode)
|
||||
&& rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
|
||||
{
|
||||
|
|
@ -3451,8 +3435,7 @@
|
|||
(match_operand:GPR 2 "const_int_operand" "n")))]
|
||||
"rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
|
||||
&& !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
|
||||
|| (logical_const_operand (operands[2], <MODE>mode)
|
||||
&& rs6000_gen_cell_microcode))"
|
||||
|| logical_const_operand (operands[2], <MODE>mode))"
|
||||
"#"
|
||||
"&& 1"
|
||||
[(pc)]
|
||||
|
|
@ -3470,11 +3453,9 @@
|
|||
(const_int 0)))
|
||||
(clobber (match_scratch:GPR 0 "=r,r"))]
|
||||
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
|
||||
&& rs6000_gen_cell_microcode
|
||||
&& rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
|
||||
&& !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
|
||||
|| (logical_const_operand (operands[2], <MODE>mode)
|
||||
&& rs6000_gen_cell_microcode))"
|
||||
|| logical_const_operand (operands[2], <MODE>mode))"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(pc)]
|
||||
|
|
@ -3495,11 +3476,9 @@
|
|||
(and:GPR (match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
|
||||
&& rs6000_gen_cell_microcode
|
||||
&& rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
|
||||
&& !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
|
||||
|| (logical_const_operand (operands[2], <MODE>mode)
|
||||
&& rs6000_gen_cell_microcode))"
|
||||
|| logical_const_operand (operands[2], <MODE>mode))"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(pc)]
|
||||
|
|
@ -3592,7 +3571,7 @@
|
|||
(match_operand:GPR 2 "gpc_reg_operand" "r,r")])
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:GPR 0 "=r,r"))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
%q3. %0,%1,%2
|
||||
#"
|
||||
|
|
@ -3615,7 +3594,7 @@
|
|||
(const_int 0)))
|
||||
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
|
||||
(match_dup 3))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
%q3. %0,%1,%2
|
||||
#"
|
||||
|
|
@ -3647,7 +3626,7 @@
|
|||
(match_operand:GPR 1 "gpc_reg_operand" "r,r")])
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:GPR 0 "=r,r"))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
%q3. %0,%1,%2
|
||||
#"
|
||||
|
|
@ -3670,7 +3649,7 @@
|
|||
(const_int 0)))
|
||||
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
|
||||
(match_dup 3))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
%q3. %0,%1,%2
|
||||
#"
|
||||
|
|
@ -3702,7 +3681,7 @@
|
|||
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:GPR 0 "=r,r"))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
%q3. %0,%1,%2
|
||||
#"
|
||||
|
|
@ -3725,7 +3704,7 @@
|
|||
(const_int 0)))
|
||||
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
|
||||
(match_dup 3))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
%q3. %0,%1,%2
|
||||
#"
|
||||
|
|
@ -3775,7 +3754,6 @@
|
|||
(const_int 0)))
|
||||
(clobber (match_scratch:GPR 0 "=r,r"))]
|
||||
"(<MODE>mode == Pmode || UINTVAL (operands[3]) <= 0x7fffffff)
|
||||
&& rs6000_gen_cell_microcode
|
||||
&& rs6000_is_valid_shift_mask (operands[3], operands[4], <MODE>mode)"
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
|
|
@ -3808,7 +3786,6 @@
|
|||
(and:GPR (match_dup 4)
|
||||
(match_dup 3)))]
|
||||
"(<MODE>mode == Pmode || UINTVAL (operands[3]) <= 0x7fffffff)
|
||||
&& rs6000_gen_cell_microcode
|
||||
&& rs6000_is_valid_shift_mask (operands[3], operands[4], <MODE>mode)"
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
|
|
@ -4065,7 +4042,7 @@
|
|||
(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:GPR 0 "=r,r"))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
rotl<wd>%I2. %0,%1,%<hH>2
|
||||
#"
|
||||
|
|
@ -4090,7 +4067,7 @@
|
|||
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
|
||||
(rotate:GPR (match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
rotl<wd>%I2. %0,%1,%<hH>2
|
||||
#"
|
||||
|
|
@ -4133,7 +4110,7 @@
|
|||
(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:GPR 0 "=r,r"))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
sl<wd>%I2. %0,%1,%<hH>2
|
||||
#"
|
||||
|
|
@ -4158,7 +4135,7 @@
|
|||
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
|
||||
(ashift:GPR (match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
sl<wd>%I2. %0,%1,%<hH>2
|
||||
#"
|
||||
|
|
@ -4322,7 +4299,7 @@
|
|||
(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:GPR 0 "=r,r"))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
sr<wd>%I2. %0,%1,%<hH>2
|
||||
#"
|
||||
|
|
@ -4347,7 +4324,7 @@
|
|||
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
|
||||
(lshiftrt:GPR (match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
sr<wd>%I2. %0,%1,%<hH>2
|
||||
#"
|
||||
|
|
@ -4393,7 +4370,7 @@
|
|||
(const_int 0)))
|
||||
(clobber (match_scratch:GPR 0 "=r,r"))
|
||||
(clobber (reg:GPR CA_REGNO))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
sra<wd>%I2. %0,%1,%<hH>2
|
||||
#"
|
||||
|
|
@ -4420,7 +4397,7 @@
|
|||
(ashiftrt:GPR (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:GPR CA_REGNO))]
|
||||
"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
|
||||
"<MODE>mode == Pmode"
|
||||
"@
|
||||
sra<wd>%I2. %0,%1,%<hH>2
|
||||
#"
|
||||
|
|
@ -7061,10 +7038,10 @@
|
|||
(set_attr "length" "4,4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
|
||||
(compare:CC (match_operand:P 1 "gpc_reg_operand" "")
|
||||
[(set (match_operand:CC 2 "cc_reg_not_cr0_operand")
|
||||
(compare:CC (match_operand:P 1 "gpc_reg_operand")
|
||||
(const_int 0)))
|
||||
(set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
|
||||
(set (match_operand:P 0 "gpc_reg_operand") (match_dup 1))]
|
||||
"reload_completed"
|
||||
[(set (match_dup 0) (match_dup 1))
|
||||
(set (match_dup 2)
|
||||
|
|
@ -9610,8 +9587,7 @@
|
|||
(match_operand:DI 2 "gpc_reg_operand" "r")))))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=b")
|
||||
(plus:DI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_POWERPC64 && rs6000_gen_cell_microcode
|
||||
&& !avoiding_indexed_address_p (DImode)"
|
||||
"TARGET_POWERPC64 && !avoiding_indexed_address_p (DImode)"
|
||||
"lwaux %3,%0,%2"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "sign_extend" "yes")
|
||||
|
|
@ -9692,9 +9668,9 @@
|
|||
(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_UPDATE && rs6000_gen_cell_microcode
|
||||
&& (!avoiding_indexed_address_p (SImode)
|
||||
|| !gpc_reg_operand (operands[2], SImode))"
|
||||
"TARGET_UPDATE
|
||||
&& !(avoiding_indexed_address_p (SImode)
|
||||
&& gpc_reg_operand (operands[2], SImode))"
|
||||
"@
|
||||
lhaux %3,%0,%2
|
||||
lhau %3,%2(%0)"
|
||||
|
|
@ -12300,14 +12276,14 @@
|
|||
(set_attr "length" "8,16")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
|
||||
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand")
|
||||
(compare:CC
|
||||
(ashift:SI (match_operator:SI 1 "scc_comparison_operator"
|
||||
[(match_operand 2 "cc_reg_operand" "")
|
||||
[(match_operand 2 "cc_reg_operand")
|
||||
(const_int 0)])
|
||||
(match_operand:SI 3 "const_int_operand" ""))
|
||||
(match_operand:SI 3 "const_int_operand"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 4 "gpc_reg_operand" "")
|
||||
(set (match_operand:SI 4 "gpc_reg_operand")
|
||||
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
|
||||
(match_dup 3)))]
|
||||
"reload_completed"
|
||||
|
|
|
|||
|
|
@ -441,13 +441,9 @@ mlongcall
|
|||
Target Report Var(rs6000_default_long_calls) Save
|
||||
Avoid all range limits on call instructions.
|
||||
|
||||
; This option existed in the past, but now is always on.
|
||||
mgen-cell-microcode
|
||||
Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save
|
||||
Generate Cell microcode.
|
||||
|
||||
mwarn-cell-microcode
|
||||
Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save
|
||||
Warn when a Cell microcoded instruction is emitted.
|
||||
Target RejectNegative Undocumented Ignore
|
||||
|
||||
mwarn-altivec-long
|
||||
Target Var(rs6000_warn_altivec_long) Init(1) Save
|
||||
|
|
|
|||
|
|
@ -1023,7 +1023,6 @@ See RS/6000 and PowerPC Options.
|
|||
-mspe -mno-spe @gol
|
||||
-mspe=yes -mspe=no @gol
|
||||
-mpaired @gol
|
||||
-mgen-cell-microcode -mwarn-cell-microcode @gol
|
||||
-mvrsave -mno-vrsave @gol
|
||||
-mmulhw -mno-mulhw @gol
|
||||
-mdlmzb -mno-dlmzb @gol
|
||||
|
|
@ -21281,15 +21280,6 @@ corresponding to the endianness for the target.
|
|||
@opindex mno-vrsave
|
||||
Generate VRSAVE instructions when generating AltiVec code.
|
||||
|
||||
@item -mgen-cell-microcode
|
||||
@opindex mgen-cell-microcode
|
||||
Generate Cell microcode instructions.
|
||||
|
||||
@item -mwarn-cell-microcode
|
||||
@opindex mwarn-cell-microcode
|
||||
Warn when a Cell microcode instruction is emitted. An example
|
||||
of a Cell microcode instruction is a variable shift.
|
||||
|
||||
@item -msecure-plt
|
||||
@opindex msecure-plt
|
||||
Generate code that allows @command{ld} and @command{ld.so}
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2017-05-30 Segher Boessenkool <segher@kernel.crashing.org>
|
||||
|
||||
* gcc.target/powerpc/shift-dot.c: Delete -mgen-cell-microcode from
|
||||
dg-options.
|
||||
* gfortran.dg/pr80107.f: Delete testcase.
|
||||
|
||||
2017-05-30 Uros Bizjak <ubizjak@gmail.com>
|
||||
|
||||
PR target/80833
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/* Check that record-form instructions are used. */
|
||||
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mgen-cell-microcode" } */
|
||||
/* { dg-options "-O2" } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mrotl[wd]\.} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\msl[wd]\.} 2 } } */
|
||||
|
|
|
|||
|
|
@ -1,6 +0,0 @@
|
|||
! { dg-do compile { target { powerpc*-*-* } } }
|
||||
! { dg-options "-O0 -mpower9-dform-vector -mno-gen-cell-microcode" }
|
||||
|
||||
integer(kind=2) j, j2, ja
|
||||
call c_c(CMPLX(j),(1.,0.),'CMPLX(integer(2))')
|
||||
end
|
||||
Loading…
Add table
Reference in a new issue