Support 2-instruction vector shuffle for V4SI/V4SF in ix86_expand_vec_perm_const_1.
2022-09-23 Hongtao Liu <hongtao.liu@intel.com> Liwei Xu <liwei.xu@intel.com> gcc/ChangeLog: PR target/53346 * config/i386/i386-expand.cc (expand_vec_perm_shufps_shufps): New function. (ix86_expand_vec_perm_const_1): Insert expand_vec_perm_shufps_shufps at the end of 2-instruction expand sequence. gcc/testsuite/ChangeLog: * gcc.target/i386/pr53346-1.c: New test. * gcc.target/i386/pr53346-2.c: New test. * gcc.target/i386/pr53346-3.c: New test. * gcc.target/i386/pr53346-4.c: New test.
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5 changed files with 373 additions and 0 deletions
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@ -19604,6 +19604,119 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d)
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return false;
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}
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/* A subroutine of ix86_expand_vec_perm_const_1. Try to implement D
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in terms of a pair of shufps+ shufps/pshufd instructions. */
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static bool
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expand_vec_perm_shufps_shufps (struct expand_vec_perm_d *d)
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{
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unsigned char perm1[4];
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machine_mode vmode = d->vmode;
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bool ok;
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unsigned i, j, k, count = 0;
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if (d->one_operand_p
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|| (vmode != V4SImode && vmode != V4SFmode))
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return false;
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if (d->testing_p)
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return true;
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for (i = 0; i < 4; ++i)
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count += d->perm[i] > 3 ? 1 : 0;
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gcc_assert (count & 3);
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rtx tmp = gen_reg_rtx (vmode);
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/* 2 from op0 and 2 from op1. */
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if (count == 2)
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{
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unsigned char perm2[4];
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for (i = 0, j = 0, k = 2; i < 4; ++i)
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if (d->perm[i] & 4)
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{
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perm1[k++] = d->perm[i];
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perm2[i] = k - 1;
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}
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else
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{
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perm1[j++] = d->perm[i];
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perm2[i] = j - 1;
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}
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/* shufps. */
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ok = expand_vselect_vconcat (tmp, d->op0, d->op1,
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perm1, d->nelt, false);
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gcc_assert (ok);
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if (vmode == V4SImode && TARGET_SSE2)
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/* pshufd. */
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ok = expand_vselect (d->target, tmp,
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perm2, d->nelt, false);
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else
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{
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/* shufps. */
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perm2[2] += 4;
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perm2[3] += 4;
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ok = expand_vselect_vconcat (d->target, tmp, tmp,
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perm2, d->nelt, false);
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}
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gcc_assert (ok);
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}
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/* 3 from one op and 1 from another. */
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else
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{
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unsigned pair_idx = 8, lone_idx = 8, shift;
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/* Find the lone index. */
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for (i = 0; i < 4; ++i)
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if ((d->perm[i] > 3 && count == 1)
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|| (d->perm[i] < 4 && count == 3))
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lone_idx = i;
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/* When lone_idx is not 0, it must from second op(count == 1). */
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gcc_assert (count == (lone_idx ? 1 : 3));
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/* Find the pair index that sits in the same half as the lone index. */
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shift = lone_idx & 2;
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pair_idx = 1 - lone_idx + 2 * shift;
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/* First permutate lone index and pair index into the same vector as
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[ lone, lone, pair, pair ]. */
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perm1[1] = perm1[0]
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= (count == 3) ? d->perm[lone_idx] : d->perm[lone_idx] - 4;
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perm1[3] = perm1[2]
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= (count == 3) ? d->perm[pair_idx] : d->perm[pair_idx] + 4;
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/* Alway put the vector contains lone indx at the first. */
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if (count == 1)
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std::swap (d->op0, d->op1);
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/* shufps. */
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ok = expand_vselect_vconcat (tmp, d->op0, d->op1,
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perm1, d->nelt, false);
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gcc_assert (ok);
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/* Refine lone and pair index to original order. */
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perm1[shift] = lone_idx << 1;
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perm1[shift + 1] = pair_idx << 1;
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/* Select the remaining 2 elements in another vector. */
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for (i = 2 - shift; i < 4 - shift; ++i)
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perm1[i] = lone_idx == 1 ? d->perm[i] + 4 : d->perm[i];
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/* Adjust to original selector. */
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if (lone_idx > 1)
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std::swap (tmp, d->op1);
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/* shufps. */
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ok = expand_vselect_vconcat (d->target, tmp, d->op1,
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perm1, d->nelt, false);
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gcc_assert (ok);
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}
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return true;
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}
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/* A subroutine of ix86_expand_vec_perm_const_1. Try to implement D
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in terms of a pair of pshuflw + pshufhw instructions. */
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@ -22152,6 +22265,9 @@ ix86_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
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if (expand_vec_perm_2perm_pblendv (d, true))
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return true;
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if (expand_vec_perm_shufps_shufps (d))
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return true;
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/* Try sequences of three instructions. */
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if (expand_vec_perm_even_odd_pack (d))
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70
gcc/testsuite/gcc.target/i386/pr53346-1.c
Normal file
70
gcc/testsuite/gcc.target/i386/pr53346-1.c
Normal file
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@ -0,0 +1,70 @@
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/* { dg-do compile } */
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/* { dg-options "-msse2 -O2 -mno-sse3" } */
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/* { dg-final { scan-assembler-times "shufps" 15 } } */
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/* { dg-final { scan-assembler-times "pshufd" 2 } } */
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typedef int v4si __attribute__((vector_size(16)));
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v4si
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__attribute__((noipa))
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foo (v4si a, v4si b)
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{
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return __builtin_shufflevector (a, b, 1, 2, 5, 3);
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}
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v4si
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__attribute__((noipa))
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foo1 (v4si a, v4si b)
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{
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return __builtin_shufflevector (a, b, 1, 5, 2, 3);
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}
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v4si
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__attribute__((noipa))
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foo2 (v4si a, v4si b)
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{
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return __builtin_shufflevector (a, b, 1, 2, 3, 5);
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}
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v4si
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__attribute__((noipa))
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foo3 (v4si a, v4si b)
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{
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return __builtin_shufflevector (a, b, 1, 4, 5, 6);
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}
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v4si
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__attribute__((noipa))
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foo4 (v4si a, v4si b)
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{
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return __builtin_shufflevector (a, b, 3, 6, 7, 5);
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}
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v4si
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__attribute__((noipa))
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foo5 (v4si a, v4si b)
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{
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return __builtin_shufflevector (a, b, 2, 4, 7, 6);
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}
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v4si
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__attribute__((noipa))
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foo6 (v4si a, v4si b)
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{
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return __builtin_shufflevector (a, b, 2, 4, 3, 6);
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}
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v4si
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__attribute__((noipa))
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foo7 (v4si a, v4si b)
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{
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return __builtin_shufflevector (a, b, 2, 3, 4, 6);
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}
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v4si
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__attribute__((noipa))
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foo8 (v4si a, v4si b)
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{
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return __builtin_shufflevector (a, b, 2, 4, 6, 3);
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}
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59
gcc/testsuite/gcc.target/i386/pr53346-2.c
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59
gcc/testsuite/gcc.target/i386/pr53346-2.c
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@ -0,0 +1,59 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -msse2" } */
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/* { dg-require-effective-target sse2 } */
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#include "sse2-check.h"
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#include "pr53346-1.c"
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static void
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sse2_test ()
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{
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v4si a = __extension__(v4si) { 0, 1, 2, 3 };
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v4si b = __extension__(v4si) { 4, 5, 6, 7 };
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v4si exp = __extension__(v4si) { 1, 2, 5, 3 };
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v4si dest;
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dest = foo (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4si) { 1, 5, 2, 3 };
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dest = foo1 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4si) { 1, 2, 3, 5 };
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dest = foo2 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4si) { 1, 4, 5, 6 };
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dest = foo3 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4si) { 3, 6, 7, 5 };
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dest = foo4 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4si) { 2, 4, 7, 6 };
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dest = foo5 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4si) { 2, 4, 3, 6 };
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dest = foo6 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4si) { 2, 3, 4, 6 };
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dest = foo7 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4si) { 2, 4, 6, 3 };
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dest = foo8 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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}
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69
gcc/testsuite/gcc.target/i386/pr53346-3.c
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69
gcc/testsuite/gcc.target/i386/pr53346-3.c
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@ -0,0 +1,69 @@
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/* { dg-do compile } */
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/* { dg-options "-msse2 -O2 -mno-sse3" } */
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/* { dg-final { scan-assembler-times "shufps" 17 } } */
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typedef float v4sf __attribute__((vector_size(16)));
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v4sf
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__attribute__((noipa))
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foo (v4sf a, v4sf b)
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{
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return __builtin_shufflevector (a, b, 1, 2, 5, 3);
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}
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v4sf
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__attribute__((noipa))
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foo1 (v4sf a, v4sf b)
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{
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return __builtin_shufflevector (a, b, 1, 5, 2, 3);
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}
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v4sf
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__attribute__((noipa))
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foo2 (v4sf a, v4sf b)
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{
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return __builtin_shufflevector (a, b, 1, 2, 3, 5);
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}
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v4sf
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__attribute__((noipa))
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foo3 (v4sf a, v4sf b)
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{
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return __builtin_shufflevector (a, b, 1, 4, 5, 6);
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}
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v4sf
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__attribute__((noipa))
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foo4 (v4sf a, v4sf b)
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{
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return __builtin_shufflevector (a, b, 3, 6, 7, 5);
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}
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v4sf
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__attribute__((noipa))
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foo5 (v4sf a, v4sf b)
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{
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return __builtin_shufflevector (a, b, 2, 4, 7, 6);
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}
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v4sf
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__attribute__((noipa))
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foo6 (v4sf a, v4sf b)
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{
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return __builtin_shufflevector (a, b, 2, 4, 3, 6);
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}
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v4sf
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__attribute__((noipa))
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foo7 (v4sf a, v4sf b)
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{
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return __builtin_shufflevector (a, b, 2, 3, 4, 6);
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}
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v4sf
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__attribute__((noipa))
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foo8 (v4sf a, v4sf b)
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{
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return __builtin_shufflevector (a, b, 2, 4, 6, 3);
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}
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59
gcc/testsuite/gcc.target/i386/pr53346-4.c
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59
gcc/testsuite/gcc.target/i386/pr53346-4.c
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@ -0,0 +1,59 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -msse2" } */
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/* { dg-require-effective-target sse2 } */
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#include "sse2-check.h"
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#include "pr53346-3.c"
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static void
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sse2_test ()
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{
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v4sf a = __extension__(v4sf) { 0, 1, 2, 3 };
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v4sf b = __extension__(v4sf) { 4, 5, 6, 7 };
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v4sf exp = __extension__(v4sf) { 1, 2, 5, 3 };
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v4sf dest;
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dest = foo (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4sf) { 1, 5, 2, 3 };
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dest = foo1 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4sf) { 1, 2, 3, 5 };
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dest = foo2 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4sf) { 1, 4, 5, 6 };
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dest = foo3 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4sf) { 3, 6, 7, 5 };
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dest = foo4 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4sf) { 2, 4, 7, 6 };
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dest = foo5 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4sf) { 2, 4, 3, 6 };
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dest = foo6 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4sf) { 2, 3, 4, 6 };
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dest = foo7 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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exp = __extension__ (v4sf) { 2, 4, 6, 3 };
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dest = foo8 (a, b);
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if (__builtin_memcmp (&dest, &exp, 16))
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__builtin_abort ();
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}
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