RISC-V: Add vasub.vx C++ API tests
gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vasub_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vasub_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vasub_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vasub_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vasub_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vasub_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vasub_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vasub_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vasub_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vasub_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vasub_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vasub_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-3.C: New test.
This commit is contained in:
Ju-Zhe Zhong
Kito Cheng
parent
1a8c69e7ea
commit
3d65ea07b4
30 changed files with 5670 additions and 0 deletions
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv32-1.C
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157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv32-1.C
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/* { dg-do compile } */
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/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
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#include "riscv_vector.h"
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vint8mf8_t test___riscv_vasub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint8mf4_t test___riscv_vasub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint8mf2_t test___riscv_vasub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint8m1_t test___riscv_vasub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint8m2_t test___riscv_vasub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint8m4_t test___riscv_vasub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint8m8_t test___riscv_vasub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint16mf4_t test___riscv_vasub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint16mf2_t test___riscv_vasub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint16m1_t test___riscv_vasub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint16m2_t test___riscv_vasub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint16m4_t test___riscv_vasub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint16m8_t test___riscv_vasub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint32mf2_t test___riscv_vasub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint32m1_t test___riscv_vasub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint32m2_t test___riscv_vasub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint32m4_t test___riscv_vasub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint32m8_t test___riscv_vasub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint64m1_t test___riscv_vasub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint64m2_t test___riscv_vasub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint64m4_t test___riscv_vasub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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vint64m8_t test___riscv_vasub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,vl);
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}
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
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157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv32-2.C
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gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv32-2.C
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/* { dg-do compile } */
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/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
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#include "riscv_vector.h"
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vint8mf8_t test___riscv_vasub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint8mf4_t test___riscv_vasub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint8mf2_t test___riscv_vasub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint8m1_t test___riscv_vasub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint8m2_t test___riscv_vasub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint8m4_t test___riscv_vasub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint8m8_t test___riscv_vasub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint16mf4_t test___riscv_vasub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint16mf2_t test___riscv_vasub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint16m1_t test___riscv_vasub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint16m2_t test___riscv_vasub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint16m4_t test___riscv_vasub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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vint16m8_t test___riscv_vasub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
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{
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return __riscv_vasub_mu(mask,merge,op1,op2,31);
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}
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||||
|
||||
vint32mf2_t test___riscv_vasub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv32-3.C
Normal file
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv32-3.C
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv64-1.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv64-1.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv64-2.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv64-2.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv64-3.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv64-3.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
308
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv32-1.C
Normal file
308
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv32-1.C
Normal file
|
|
@ -0,0 +1,308 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
308
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv32-2.C
Normal file
308
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv32-2.C
Normal file
|
|
@ -0,0 +1,308 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
308
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv32-3.C
Normal file
308
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv32-3.C
Normal file
|
|
@ -0,0 +1,308 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
314
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv64-1.C
Normal file
314
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv64-1.C
Normal file
|
|
@ -0,0 +1,314 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
314
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv64-2.C
Normal file
314
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv64-2.C
Normal file
|
|
@ -0,0 +1,314 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
314
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv64-3.C
Normal file
314
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv64-3.C
Normal file
|
|
@ -0,0 +1,314 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf8_t test___riscv_vasub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv32-1.C
Normal file
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv32-1.C
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
|
||||
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv32-2.C
Normal file
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv32-2.C
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
|
||||
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv32-3.C
Normal file
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv32-3.C
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv64-1.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv64-1.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv64-2.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv64-2.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv64-3.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv64-3.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv32-1.C
Normal file
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv32-1.C
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv32-2.C
Normal file
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv32-2.C
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv32-3.C
Normal file
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv32-3.C
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv64-1.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv64-1.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv64-2.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv64-2.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv64-3.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv64-3.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-1.C
Normal file
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-1.C
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-2.C
Normal file
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-2.C
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-3.C
Normal file
157
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-3.C
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vasub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-1.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-1.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-2.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-2.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-3.C
Normal file
160
gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-3.C
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vint8mf8_t test___riscv_vasub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf4_t test___riscv_vasub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8mf2_t test___riscv_vasub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m1_t test___riscv_vasub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m2_t test___riscv_vasub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m4_t test___riscv_vasub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint8m8_t test___riscv_vasub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf4_t test___riscv_vasub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16mf2_t test___riscv_vasub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m1_t test___riscv_vasub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m2_t test___riscv_vasub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m4_t test___riscv_vasub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint16m8_t test___riscv_vasub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32mf2_t test___riscv_vasub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m1_t test___riscv_vasub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m2_t test___riscv_vasub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m4_t test___riscv_vasub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint32m8_t test___riscv_vasub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m1_t test___riscv_vasub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m2_t test___riscv_vasub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m4_t test___riscv_vasub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vint64m8_t test___riscv_vasub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vasub_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vasub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
Loading…
Add table
Reference in a new issue