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pa.md (non-canonical shift-add insns): Remove.

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* config/pa/pa.md (non-canonical shift-add insns): Remove.
	(peepholes with non-canonical RTL sources): Remove.
	(peepholes for indexed stores of FP regs in integer modes): Match and
	generate canonical RTL.

From-SVN: r223592
This commit is contained in:
Jeff Law 2015-05-22 15:25:26 -06:00 • committed by Jeff Law
parent 257b01ba3e
commit 3b0244cc3b
2 changed files with 36 additions and 137 deletions
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11
gcc/ChangeLog
View file

@ -1,3 +1,10 @@
2015-05-22 Jeff Law <law@redhat.com>
* config/pa/pa.md (non-canonical shift-add insns): Remove.
(peepholes with non-canonical RTL sources): Remove.
(peepholes for indexed stores of FP regs in integer modes): Match and
generate canonical RTL.
2015-05-22 Marc Glisse <marc.glisse@inria.fr>
PR tree-optimization/63387
@ -26,8 +33,8 @@
* combine.c (try_combine): Canonicalize (plus (mult X pow2) Y) into
(plus (ashift X log2) Y) if it is a split point.
* pa.c (mem_shadd_or_shadd_rtx_p): New function factored out
of hppa_legitimize_address to handle both forms of a multiply
* config/pa/pa.c (mem_shadd_or_shadd_rtx_p): New function factoredx
out of hppa_legitimize_address to handle both forms of a multiply
by 2, 4 or 8.
(hppa_legitimize_address): Use mem_shadd_or_shadd_rtx_p.
Always generate the ASHIFT variant as the result is not directly

162
gcc/config/pa/pa.md
View file

@ -2270,8 +2270,8 @@
; computes the address to be deleted if the register it sets is dead.
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
(const_int 4))
(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
(const_int 2))
(match_operand:SI 2 "register_operand" "")))
(set (mem:SI (match_dup 0))
(match_operand:SI 3 "register_operand" ""))]
@ -2281,31 +2281,14 @@
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
(match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 2 "register_operand" "")
(mult:SI (match_operand:SI 1 "register_operand" "")
(const_int 4))))
(set (mem:SI (match_dup 0))
(match_operand:SI 3 "register_operand" ""))]
"!TARGET_SOFT_FLOAT
&& !TARGET_DISABLE_INDEXING
&& REG_OK_FOR_BASE_P (operands[2])
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
(set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 2))
(match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
(const_int 4))
(plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
(const_int 2))
(match_operand:DI 2 "register_operand" "")))
(set (mem:SI (match_dup 0))
(match_operand:SI 3 "register_operand" ""))]
@ -2316,25 +2299,7 @@
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
(match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 2 "register_operand" "")
(mult:DI (match_operand:DI 1 "register_operand" "")
(const_int 4))))
(set (mem:SI (match_dup 0))
(match_operand:SI 3 "register_operand" ""))]
"!TARGET_SOFT_FLOAT
&& !TARGET_DISABLE_INDEXING
&& TARGET_64BIT
&& REG_OK_FOR_BASE_P (operands[2])
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 2))
(match_dup 2)))]
"")
@ -3896,8 +3861,8 @@
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
(const_int 8))
(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
(const_int 3))
(match_operand:SI 2 "register_operand" "")))
(set (mem:DF (match_dup 0))
(match_operand:DF 3 "register_operand" ""))]
@ -3907,15 +3872,15 @@
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
(set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 3))
(match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 2 "register_operand" "")
(mult:SI (match_operand:SI 1 "register_operand" "")
(const_int 8))))
(ashift:SI (match_operand:SI 1 "register_operand" "")
(const_int 3))))
(set (mem:DF (match_dup 0))
(match_operand:DF 3 "register_operand" ""))]
"!TARGET_SOFT_FLOAT
@ -3924,14 +3889,14 @@
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
(set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 3))
(match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
(const_int 8))
(plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
(const_int 3))
(match_operand:DI 2 "register_operand" "")))
(set (mem:DF (match_dup 0))
(match_operand:DF 3 "register_operand" ""))]
@ -3942,15 +3907,15 @@
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 3))
(match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 2 "register_operand" "")
(mult:DI (match_operand:DI 1 "register_operand" "")
(const_int 8))))
(ashift:DI (match_operand:DI 1 "register_operand" "")
(const_int 3))))
(set (mem:DF (match_dup 0))
(match_operand:DF 3 "register_operand" ""))]
"!TARGET_SOFT_FLOAT
@ -3960,7 +3925,7 @@
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 3))
(match_dup 2)))]
"")
@ -4244,8 +4209,8 @@
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
(const_int 8))
(plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
(const_int 3))
(match_operand:DI 2 "register_operand" "")))
(set (mem:DI (match_dup 0))
(match_operand:DI 3 "register_operand" ""))]
@ -4256,25 +4221,7 @@
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
(match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 2 "register_operand" "")
(mult:DI (match_operand:DI 1 "register_operand" "")
(const_int 8))))
(set (mem:DI (match_dup 0))
(match_operand:DI 3 "register_operand" ""))]
"!TARGET_SOFT_FLOAT
&& !TARGET_DISABLE_INDEXING
&& TARGET_64BIT
&& REG_OK_FOR_BASE_P (operands[2])
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 3))
(match_dup 2)))]
"")
@ -4466,8 +4413,8 @@
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
(const_int 4))
(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
(const_int 2))
(match_operand:SI 2 "register_operand" "")))
(set (mem:SF (match_dup 0))
(match_operand:SF 3 "register_operand" ""))]
@ -4477,31 +4424,14 @@
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
(match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 2 "register_operand" "")
(mult:SI (match_operand:SI 1 "register_operand" "")
(const_int 4))))
(set (mem:SF (match_dup 0))
(match_operand:SF 3 "register_operand" ""))]
"!TARGET_SOFT_FLOAT
&& !TARGET_DISABLE_INDEXING
&& REG_OK_FOR_BASE_P (operands[2])
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
(set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 2))
(match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
(const_int 4))
(plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
(const_int 2))
(match_operand:DI 2 "register_operand" "")))
(set (mem:SF (match_dup 0))
(match_operand:SF 3 "register_operand" ""))]
@ -4512,25 +4442,7 @@
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
(match_dup 2)))]
"")
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 2 "register_operand" "")
(mult:DI (match_operand:DI 1 "register_operand" "")
(const_int 4))))
(set (mem:SF (match_dup 0))
(match_operand:SF 3 "register_operand" ""))]
"!TARGET_SOFT_FLOAT
&& !TARGET_DISABLE_INDEXING
&& TARGET_64BIT
&& REG_OK_FOR_BASE_P (operands[2])
&& FP_REGNO_P (REGNO (operands[3]))"
[(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
(match_dup 3))
(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 2))
(match_dup 2)))]
"")
@ -6346,26 +6258,6 @@
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "mem_shadd_operand" ""))
(match_operand:SI 1 "register_operand" "r")))]
""
"{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
[(set_attr "type" "binary")
(set_attr "length" "4")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
(match_operand:DI 3 "mem_shadd_operand" ""))
(match_operand:DI 1 "register_operand" "r")))]
"TARGET_64BIT"
"shladd,l %2,%O3,%1,%0"
[(set_attr "type" "binary")
(set_attr "length" "4")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")