arm: Revert Auto-vectorization for MVE: add pack/unpack patterns PR target/104882
This reverts commit r12-1434-g046a3beb1673bf to fix PR target/104882. As discussed in the PR, it turns out that the MVE ISA has no natural mapping with GCC's vec_pack_trunc / vec_unpack standard patterns, unlike Neon or SVE for instance. This patch also adds the executable testcase provided in the PR. This test passes at -O3 because the generated code does not need to use the pack/unpack patterns, hence the use of -O2 which now triggers vectorization since a few months ago. 2022-03-18 Christophe Lyon <christohe.lyon@arm.com> PR target/104882 Revert 2021-06-11 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/mve.md (mve_vec_unpack<US>_lo_<mode>): Delete. (mve_vec_unpack<US>_hi_<mode>): Delete. (@mve_vec_pack_trunc_lo_<mode>): Delete. (mve_vmovntq_<supf><mode>): Remove '@' prefix. * config/arm/neon.md (vec_unpack<US>_hi_<mode>): Move back from vec-common.md. (vec_unpack<US>_lo_<mode>): Likewise. (vec_pack_trunc_<mode>): Rename from neon_quad_vec_pack_trunc_<mode>. * config/arm/vec-common.md (vec_unpack<US>_hi_<mode>): Delete. (vec_unpack<US>_lo_<mode>): Delete. (vec_pack_trunc_<mode>): Delete. PR target/104882 gcc/testsuite/ * gcc.target/arm/simd/mve-vclz.c: Update expected results. * gcc.target/arm/simd/mve-vshl.c: Likewise. * gcc.target/arm/simd/mve-vec-pack.c: Delete. * gcc.target/arm/simd/mve-vec-unpack.c: Delete. * gcc.target/arm/simd/pr104882.c: New test.
This commit is contained in:
Christophe Lyon
parent
25725506b8
commit
3ab5c8cd03
8 changed files with 59 additions and 169 deletions
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@ -535,26 +535,6 @@
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[(set_attr "type" "mve_move")
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])
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(define_insn "mve_vec_unpack<US>_lo_<mode>"
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[(set (match_operand:<V_unpack> 0 "register_operand" "=w")
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(SE:<V_unpack> (vec_select:<V_HALF>
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(match_operand:MVE_3 1 "register_operand" "w")
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(match_operand:MVE_3 2 "vect_par_constant_low" ""))))]
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"TARGET_HAVE_MVE"
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"vmovlb.<US>%#<V_sz_elem> %q0, %q1"
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[(set_attr "type" "mve_move")]
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)
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(define_insn "mve_vec_unpack<US>_hi_<mode>"
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[(set (match_operand:<V_unpack> 0 "register_operand" "=w")
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(SE:<V_unpack> (vec_select:<V_HALF>
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(match_operand:MVE_3 1 "register_operand" "w")
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(match_operand:MVE_3 2 "vect_par_constant_high" ""))))]
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"TARGET_HAVE_MVE"
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"vmovlt.<US>%#<V_sz_elem> %q0, %q1"
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[(set_attr "type" "mve_move")]
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)
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;;
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;; [vcvtpq_s, vcvtpq_u])
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;;
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@ -2219,23 +2199,10 @@
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[(set_attr "type" "mve_move")
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])
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;; vmovnb pattern used by the vec_pack_trunc expander to avoid the
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;; need for an uninitialized input operand.
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(define_insn "@mve_vec_pack_trunc_lo_<mode>"
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[
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(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
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(unspec:<V_narrow_pack> [(match_operand:MVE_5 1 "s_register_operand" "w")]
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VMOVNBQ_S))
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]
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"TARGET_HAVE_MVE"
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"vmovnb.i%#<V_sz_elem> %q0, %q1"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vmovntq_s, vmovntq_u])
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;;
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(define_insn "@mve_vmovntq_<supf><mode>"
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(define_insn "mve_vmovntq_<supf><mode>"
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[
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(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
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(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
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@ -6005,6 +6005,43 @@ if (BYTES_BIG_ENDIAN)
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[(set_attr "type" "neon_shift_imm_long")]
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)
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(define_expand "vec_unpack<US>_hi_<mode>"
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[(match_operand:<V_unpack> 0 "register_operand")
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(SE:<V_unpack> (match_operand:VU 1 "register_operand"))]
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"TARGET_NEON && !BYTES_BIG_ENDIAN"
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{
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rtvec v = rtvec_alloc (<V_mode_nunits>/2) ;
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rtx t1;
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int i;
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for (i = 0; i < (<V_mode_nunits>/2); i++)
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RTVEC_ELT (v, i) = GEN_INT ((<V_mode_nunits>/2) + i);
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t1 = gen_rtx_PARALLEL (<MODE>mode, v);
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emit_insn (gen_neon_vec_unpack<US>_hi_<mode> (operands[0],
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operands[1],
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t1));
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DONE;
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}
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)
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(define_expand "vec_unpack<US>_lo_<mode>"
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[(match_operand:<V_unpack> 0 "register_operand")
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(SE:<V_unpack> (match_operand:VU 1 "register_operand"))]
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"TARGET_NEON && !BYTES_BIG_ENDIAN"
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{
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rtvec v = rtvec_alloc (<V_mode_nunits>/2) ;
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rtx t1;
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int i;
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for (i = 0; i < (<V_mode_nunits>/2) ; i++)
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RTVEC_ELT (v, i) = GEN_INT (i);
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t1 = gen_rtx_PARALLEL (<MODE>mode, v);
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emit_insn (gen_neon_vec_unpack<US>_lo_<mode> (operands[0],
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operands[1],
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t1));
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DONE;
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}
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)
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(define_insn "neon_vec_<US>mult_lo_<mode>"
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[(set (match_operand:<V_unpack> 0 "register_operand" "=w")
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(mult:<V_unpack> (SE:<V_unpack> (vec_select:<V_HALF>
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@ -6220,7 +6257,7 @@ if (BYTES_BIG_ENDIAN)
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; because the ordering of vector elements in Q registers is different from what
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; the semantics of the instructions require.
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(define_insn "neon_quad_vec_pack_trunc_<mode>"
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(define_insn "vec_pack_trunc_<mode>"
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[(set (match_operand:<V_narrow_pack> 0 "register_operand" "=&w")
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(vec_concat:<V_narrow_pack>
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(truncate:<V_narrow>
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@ -580,77 +580,6 @@
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"ARM_HAVE_<MODE>_ARITH
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&& !TARGET_REALLY_IWMMXT"
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)
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;; vmovl[tb] are not available for V4SI on MVE
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(define_expand "vec_unpack<US>_hi_<mode>"
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[(set (match_operand:<V_unpack> 0 "register_operand")
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(SE:<V_unpack> (vec_select:<V_HALF>
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(match_operand:VU 1 "register_operand")
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(match_dup 2))))]
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"ARM_HAVE_<MODE>_ARITH
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&& !TARGET_REALLY_IWMMXT
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&& ! (<MODE>mode == V4SImode && TARGET_HAVE_MVE)
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&& !BYTES_BIG_ENDIAN"
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{
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rtvec v = rtvec_alloc (<V_mode_nunits>/2);
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int i;
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for (i = 0; i < (<V_mode_nunits>/2); i++)
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RTVEC_ELT (v, i) = GEN_INT ((<V_mode_nunits>/2) + i);
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operands[2] = gen_rtx_PARALLEL (<MODE>mode, v);
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}
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)
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;; vmovl[tb] are not available for V4SI on MVE
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(define_expand "vec_unpack<US>_lo_<mode>"
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[(set (match_operand:<V_unpack> 0 "register_operand")
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(SE:<V_unpack> (vec_select:<V_HALF>
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(match_operand:VU 1 "register_operand")
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(match_dup 2))))]
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"ARM_HAVE_<MODE>_ARITH
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&& !TARGET_REALLY_IWMMXT
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&& ! (<MODE>mode == V4SImode && TARGET_HAVE_MVE)
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&& !BYTES_BIG_ENDIAN"
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{
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rtvec v = rtvec_alloc (<V_mode_nunits>/2);
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int i;
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for (i = 0; i < (<V_mode_nunits>/2) ; i++)
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RTVEC_ELT (v, i) = GEN_INT (i);
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operands[2] = gen_rtx_PARALLEL (<MODE>mode, v);
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}
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)
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;; vmovn[tb] are not available for V2DI on MVE
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(define_expand "vec_pack_trunc_<mode>"
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[(set (match_operand:<V_narrow_pack> 0 "register_operand")
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(vec_concat:<V_narrow_pack>
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(truncate:<V_narrow>
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(match_operand:VN 1 "register_operand"))
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(truncate:<V_narrow>
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(match_operand:VN 2 "register_operand"))))]
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"ARM_HAVE_<MODE>_ARITH
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&& !TARGET_REALLY_IWMMXT
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&& ! (<MODE>mode == V2DImode && TARGET_HAVE_MVE)
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&& !BYTES_BIG_ENDIAN"
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{
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if (TARGET_NEON)
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{
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emit_insn (gen_neon_quad_vec_pack_trunc_<mode> (operands[0], operands[1],
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operands[2]));
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}
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else
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{
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rtx tmpreg = gen_reg_rtx (<V_narrow_pack>mode);
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emit_insn (gen_mve_vec_pack_trunc_lo (<MODE>mode, tmpreg, operands[1]));
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emit_insn (gen_mve_vmovntq (VMOVNTQ_S, <MODE>mode,
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operands[0], tmpreg, operands[2]));
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}
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DONE;
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}
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)
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(define_expand "vec_init<mode><V_elem_l>"
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[(match_operand:VDQX 0 "s_register_operand")
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(match_operand 1 "" "")]
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@ -21,9 +21,8 @@ FUNC(u, uint, 16, clz)
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FUNC(s, int, 8, clz)
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FUNC(u, uint, 8, clz)
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/* 16 and 8-bit versions still use 32-bit intermediate temporaries, so for
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instance instead of using vclz.i8, we need 4 vclz.i32, leading to a total of
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14 vclz.i32 expected in this testcase. */
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/* { dg-final { scan-assembler-times {vclz\.i32 q[0-9]+, q[0-9]+} 14 } } */
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/* 16 and 8-bit versions are not vectorized because they need pack/unpack
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patterns since __builtin_clz uses 32-bit parameter and return value. */
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/* { dg-final { scan-assembler-times {vclz\.i32 q[0-9]+, q[0-9]+} 2 } } */
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/* { dg-final { scan-assembler-times {vclz\.i16 q[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {vclz\.i8 q[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */
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@ -1,26 +0,0 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target arm_v8_1m_mve_ok } */
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/* { dg-add-options arm_v8_1m_mve } */
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/* { dg-additional-options "-O3" } */
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#include <stdint.h>
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#define FUNC(SIGN, TYPE, DSTBITS, BITS, NAME) \
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void test_ ## NAME ##_ ## SIGN ## BITS (TYPE##DSTBITS##_t * __restrict__ dest, \
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TYPE##BITS##_t *a) { \
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int i; \
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for (i=0; i < (256 / BITS); i++) { \
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dest[i] = a[i]; \
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} \
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}
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FUNC(s, int, 16, 32, pack)
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FUNC(u, uint, 16, 32, pack)
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FUNC(s, int, 8, 16, pack)
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FUNC(u, uint, 8, 16, pack)
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/* { dg-final { scan-assembler-times {vmovnt\.i32\tq[0-9]+, q[0-9]+} 2 } } */
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/* { dg-final { scan-assembler-times {vmovnb\.i32\tq[0-9]+, q[0-9]+} 2 } } */
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/* { dg-final { scan-assembler-times {vmovnt\.i16\tq[0-9]+, q[0-9]+} 2 } } */
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/* { dg-final { scan-assembler-times {vmovnb\.i16\tq[0-9]+, q[0-9]+} 2 } } */
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/* { dg-final { scan-assembler-not {vldr\.64\td[0-9]+, \.L} } } */
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@ -1,29 +0,0 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target arm_v8_1m_mve_ok } */
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/* { dg-add-options arm_v8_1m_mve } */
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/* { dg-additional-options "-O3" } */
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#include <stdint.h>
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#define FUNC(SIGN, TYPE, DSTBITS, BITS, NAME) \
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void test_ ## NAME ##_ ## SIGN ## BITS (TYPE##DSTBITS##_t * __restrict__ dest, \
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TYPE##BITS##_t *a) { \
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int i; \
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for (i=0; i < (128 / BITS); i++) { \
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dest[i] = a[i]; \
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} \
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}
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FUNC(s, int, 32, 16, unpack)
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FUNC(u, uint, 32, 16, unpack)
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FUNC(s, int, 16, 8, unpack)
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FUNC(u, uint, 16, 8, unpack)
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/* { dg-final { scan-assembler-times {vmovlt\.s16 q[0-9]+, q[0-9]+} 1 } } */
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/* { dg-final { scan-assembler-times {vmovlb\.s16 q[0-9]+, q[0-9]+} 1 } } */
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/* { dg-final { scan-assembler-times {vmovlt\.u16 q[0-9]+, q[0-9]+} 1 } } */
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/* { dg-final { scan-assembler-times {vmovlb\.u16 q[0-9]+, q[0-9]+} 1 } } */
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/* { dg-final { scan-assembler-times {vmovlt\.s8 q[0-9]+, q[0-9]+} 1 } } */
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/* { dg-final { scan-assembler-times {vmovlb\.s8 q[0-9]+, q[0-9]+} 1 } } */
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/* { dg-final { scan-assembler-times {vmovlt\.u8 q[0-9]+, q[0-9]+} 1 } } */
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/* { dg-final { scan-assembler-times {vmovlb\.u8 q[0-9]+, q[0-9]+} 1 } } */
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@ -56,10 +56,7 @@ FUNC_IMM(u, uint, 8, 16, <<, vshlimm)
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/* MVE has only 128-bit vectors, so we can vectorize only half of the
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functions above. */
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/* We only emit vshl.u, which is equivalent to vshl.s anyway. */
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/* 16 and 8-bit versions still use 32-bit intermediate temporaries, so for
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instance instead of using vshl.u8, we need 4 vshl.i32, leading to a total of
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14 vshl.i32 expected in this testcase. */
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/* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 14 } } */
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/* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 2 } } */
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/* We emit vshl.i when the shift amount is an immediate. */
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/* { dg-final { scan-assembler-times {vshl.i[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */
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16
gcc/testsuite/gcc.target/arm/simd/pr104882.c
Normal file
16
gcc/testsuite/gcc.target/arm/simd/pr104882.c
Normal file
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@ -0,0 +1,16 @@
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/* { dg-do run } */
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/* { dg-require-effective-target arm_v8_1m_mve_ok } */
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/* { dg-add-options arm_v8_1m_mve } */
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/* { dg-additional-options "-O2" } */
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int i;
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char src[1072];
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char dst[72];
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int main() {
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for (i = 0; i < 128; i++)
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src[i] = i;
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__builtin_memcpy(dst, src, 7);
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for (i = 0; i < 7; i++)
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if (dst[i] != i)
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__builtin_abort();
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}
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