i386: Cleanup V2QI arithmetic instructions
2022-01-13 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: * config/i386/mmx.md (negv2qi): Disparage GPR alternative a bit. Disable for TARGET_PARTIAL_REG_STALL unless optimizing for size. (negv2qi splitters): Use lowpart_subreg instead of gen_lowpart to create subreg. (<plusminus:insn>v2qi3): Disparage GPR alternative a bit. Disable for TARGET_PARTIAL_REG_STALL unless optimizing for size. (<plusminus:insn>v2qi3 splitters): Use lowpart_subreg instead of gen_lowpart to create subreg. * config/i386/i386.md (*subqi_ext<mode>_2): Move.
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Uros Bizjak
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70ba28304b
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386b15d6ef
2 changed files with 52 additions and 52 deletions
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@ -6905,6 +6905,30 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*subqi_ext<mode>_2"
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[(set (zero_extract:SWI248
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(match_operand:SWI248 0 "register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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(subreg:SWI248
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(minus:QI
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(subreg:QI
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(zero_extract:SWI248
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(match_operand:SWI248 1 "register_operand" "0")
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(const_int 8)
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(const_int 8)) 0)
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(subreg:QI
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(zero_extract:SWI248
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(match_operand:SWI248 2 "register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0)) 0))
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(clobber (reg:CC FLAGS_REG))]
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"/* FIXME: without this LRA can't reload this pattern, see PR82524. */
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rtx_equal_p (operands[0], operands[1])"
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"sub{b}\t{%h2, %h0|%h0, %h2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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;; Subtract with jump on overflow.
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(define_expand "subv<mode>4"
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[(parallel [(set (reg:CCO FLAGS_REG)
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@ -6932,30 +6956,6 @@
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operands[4] = gen_rtx_SIGN_EXTEND (<DPWI>mode, operands[2]);
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})
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(define_insn "*subqi_ext<mode>_2"
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[(set (zero_extract:SWI248
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(match_operand:SWI248 0 "register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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(subreg:SWI248
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(minus:QI
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(subreg:QI
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(zero_extract:SWI248
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(match_operand:SWI248 1 "register_operand" "0")
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(const_int 8)
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(const_int 8)) 0)
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(subreg:QI
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(zero_extract:SWI248
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(match_operand:SWI248 2 "register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0)) 0))
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(clobber (reg:CC FLAGS_REG))]
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"/* FIXME: without this LRA can't reload this pattern, see PR82524. */
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rtx_equal_p (operands[0], operands[1])"
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"sub{b}\t{%h2, %h0|%h0, %h2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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(define_insn "*subv<mode>4"
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[(set (reg:CCO FLAGS_REG)
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(eq:CCO (minus:<DWI>
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@ -1633,12 +1633,20 @@
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"TARGET_MMX_WITH_SSE"
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"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
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(define_expand "neg<mode>2"
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[(set (match_operand:VI_32 0 "register_operand")
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(minus:VI_32
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(match_dup 2)
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(match_operand:VI_32 1 "register_operand")))]
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"TARGET_SSE2"
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"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
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(define_insn "negv2qi2"
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[(set (match_operand:V2QI 0 "register_operand" "=?Q,&Yw")
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(neg:V2QI
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(match_operand:V2QI 1 "register_operand" "0,Yw")))
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(clobber (reg:CC FLAGS_REG))]
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""
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"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
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"#"
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[(set_attr "isa" "*,sse2")
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(set_attr "type" "multi")
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@ -1664,10 +1672,10 @@
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(const_int 8)) 0)) 0))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[3] = gen_lowpart (HImode, operands[1]);
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operands[2] = gen_lowpart (HImode, operands[0]);
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operands[1] = gen_lowpart (QImode, operands[1]);
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operands[0] = gen_lowpart (QImode, operands[0]);
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operands[3] = lowpart_subreg (HImode, operands[1], V2QImode);
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operands[2] = lowpart_subreg (HImode, operands[0], V2QImode);
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operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
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operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
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})
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(define_split
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@ -1678,11 +1686,11 @@
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"reload_completed"
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 0)
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(minus:V4QI (match_dup 0) (match_dup 1)))]
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(minus:V16QI (match_dup 0) (match_dup 1)))]
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{
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operands[2] = CONST0_RTX (V4QImode);
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operands[1] = gen_lowpart (V4QImode, operands[1]);
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operands[0] = gen_lowpart (V4QImode, operands[0]);
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operands[2] = CONST0_RTX (V16QImode);
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operands[1] = lowpart_subreg (V16QImode, operands[1], V2QImode);
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operands[0] = lowpart_subreg (V16QImode, operands[0], V2QImode);
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})
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(define_expand "mmx_<insn><mode>3"
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@ -1718,14 +1726,6 @@
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(set_attr "type" "mmxadd,sseadd,sseadd")
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(set_attr "mode" "DI,TI,TI")])
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(define_expand "neg<mode>2"
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[(set (match_operand:VI_32 0 "register_operand")
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(minus:VI_32
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(match_dup 2)
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(match_operand:VI_32 1 "register_operand")))]
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"TARGET_SSE2"
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"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
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(define_insn "<insn><mode>3"
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[(set (match_operand:VI_32 0 "register_operand" "=x,Yw")
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(plusminus:VI_32
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@ -1745,7 +1745,7 @@
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(match_operand:V2QI 1 "register_operand" "<comm>0,0,Yw")
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(match_operand:V2QI 2 "register_operand" "Q,x,Yw")))
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(clobber (reg:CC FLAGS_REG))]
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""
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"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
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"#"
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[(set_attr "isa" "*,sse2_noavx,avx")
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(set_attr "type" "multi,sseadd,sseadd")
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@ -1776,12 +1776,12 @@
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(const_int 8)) 0)) 0))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[5] = gen_lowpart (HImode, operands[2]);
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operands[4] = gen_lowpart (HImode, operands[1]);
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operands[3] = gen_lowpart (HImode, operands[0]);
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operands[2] = gen_lowpart (QImode, operands[2]);
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operands[1] = gen_lowpart (QImode, operands[1]);
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operands[0] = gen_lowpart (QImode, operands[0]);
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operands[5] = lowpart_subreg (HImode, operands[2], V2QImode);
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operands[4] = lowpart_subreg (HImode, operands[1], V2QImode);
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operands[3] = lowpart_subreg (HImode, operands[0], V2QImode);
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operands[2] = lowpart_subreg (QImode, operands[2], V2QImode);
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operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
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operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
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})
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(define_split
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@ -1792,11 +1792,11 @@
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_SSE2 && reload_completed"
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[(set (match_dup 0)
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(plusminus:V4QI (match_dup 1) (match_dup 2)))]
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(plusminus:V16QI (match_dup 1) (match_dup 2)))]
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{
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operands[2] = gen_lowpart (V4QImode, operands[2]);
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operands[1] = gen_lowpart (V4QImode, operands[1]);
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operands[0] = gen_lowpart (V4QImode, operands[0]);
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operands[2] = lowpart_subreg (V16QImode, operands[2], V2QImode);
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operands[1] = lowpart_subreg (V16QImode, operands[1], V2QImode);
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operands[0] = lowpart_subreg (V16QImode, operands[0], V2QImode);
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})
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(define_expand "mmx_<insn><mode>3"
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