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sh.md (cmpeqdi_t, [...]): Convert to multi-line asm output strings.

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* config/sh/sh.md (cmpeqdi_t, cmpgtdi_t, cmpgedi_t, cmpgeudi_t,
	cmpgtudi_t, *movsicc_t_false, *movsicc_t_true, divsi_inv20, negsi_cond,
	truncdihi2, ic_invalidate_line_i, ic_invalidate_line_sh4a,
	ic_invalidate_line_media, movdf_i4, calli_pcrel, call_valuei,
	call_valuei_pcrel, sibcalli_pcrel, sibcall_compact,
	sibcall_valuei_pcrel, sibcall_value_compact, casesi_worker_1,
	casesi_worker_2, bandreg_m2a, borreg_m2a, bxorreg_m2a, sp_switch_1,
	sp_switch_2, stack_protect_set_si, stack_protect_set_si_media,
	stack_protect_set_di_media, stack_protect_test_si,
	stack_protect_test_si_media, stack_protect_test_di_media): Convert to
	multi-line asm output strings.
	(divsi_inv_qitable, divsi_inv_hitable): Use single-alternative asm
	output.
	(*andsi3_bclr, rotldi3_mextr, rotrdi3_mextr, calli, call_valuei_tbr_rel,
	movml_push_banked, movml_pop_banked, bclr_m2a, bclrmem_m2a, bset_m2a,
	bsetmem_m2a, bst_m2a, bld_m2a, bldsign_m2a, bld_reg, *bld_regqi,
	band_m2a, bor_m2a, bxor_m2a, mextr_rl, *mextr_lr, ): Use tab char
	instead of '\\t'.
	(iordi3): Use braced string.
	(*movsi_pop): Use tab chars instead of spaces.

From-SVN: r190580
This commit is contained in:
Oleg Endo 2012-08-21 23:38:47 +00:00
parent 082ea1dcd5
commit 35ed5a707f
2 changed files with 351 additions and 134 deletions
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23
gcc/ChangeLog
View file

@ -1,3 +1,26 @@
2012-08-21 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.md (cmpeqdi_t, cmpgtdi_t, cmpgedi_t, cmpgeudi_t,
cmpgtudi_t, *movsicc_t_false, *movsicc_t_true, divsi_inv20, negsi_cond,
truncdihi2, ic_invalidate_line_i, ic_invalidate_line_sh4a,
ic_invalidate_line_media, movdf_i4, calli_pcrel, call_valuei,
call_valuei_pcrel, sibcalli_pcrel, sibcall_compact,
sibcall_valuei_pcrel, sibcall_value_compact, casesi_worker_1,
casesi_worker_2, bandreg_m2a, borreg_m2a, bxorreg_m2a, sp_switch_1,
sp_switch_2, stack_protect_set_si, stack_protect_set_si_media,
stack_protect_set_di_media, stack_protect_test_si,
stack_protect_test_si_media, stack_protect_test_di_media): Convert to
multi-line asm output strings.
(divsi_inv_qitable, divsi_inv_hitable): Use single-alternative asm
output.
(*andsi3_bclr, rotldi3_mextr, rotrdi3_mextr, calli, call_valuei_tbr_rel,
movml_push_banked, movml_pop_banked, bclr_m2a, bclrmem_m2a, bset_m2a,
bsetmem_m2a, bst_m2a, bld_m2a, bldsign_m2a, bld_reg, *bld_regqi,
band_m2a, bor_m2a, bxor_m2a, mextr_rl, *mextr_lr, ): Use tab char
instead of '\\t'.
(iordi3): Use braced string.
(*movsi_pop): Use tab chars instead of spaces.
2012-08-21 Oleg Endo <olegendo@gcc.gnu.org>
PR target/39423

462
gcc/config/sh/sh.md
View file

@ -541,12 +541,10 @@
;; On the SH and SH2, the rte instruction reads the return pc from the stack,
;; and thus we can't put a pop instruction in its delay slot.
;; ??? On the SH3, the rte instruction does not use the stack, so a pop
;; On the SH3 and SH4, the rte instruction does not use the stack, so a pop
;; instruction can go in the delay slot.
;; Since a normal return (rts) implicitly uses the PR register,
;; we can't allow PR register loads in an rts delay slot.
(define_delay
(eq_attr "type" "return")
[(and (eq_attr "in_delay_slot" "yes")
@ -1154,9 +1152,21 @@
(eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
(match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
"TARGET_SH1"
"@
tst %S0,%S0\;bf %,Ldi%=\;tst %R0,%R0\\n%,Ldi%=:
cmp/eq %S1,%S0\;bf %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
{
static const char* alt[] =
{
"tst %S0,%S0" "\n"
" bf 0f" "\n"
" tst %R0,%R0" "\n"
"0:",
"cmp/eq %S1,%S0" "\n"
" bf 0f" "\n"
" cmp/eq %R1,%R0" "\n"
"0:"
};
return alt[which_alternative];
}
[(set_attr "length" "6")
(set_attr "type" "arith3b")])
@ -1189,9 +1199,23 @@
(gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
(match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
"TARGET_SH2"
"@
cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
{
static const char* alt[] =
{
"cmp/eq %S1,%S0" "\n"
" bf{.|/}s 0f" "\n"
" cmp/gt %S1,%S0" "\n"
" cmp/hi %R1,%R0" "\n"
"0:",
"tst %S0,%S0" "\n"
" bf{.|/}s 0f" "\n"
" cmp/pl %S0" "\n"
" cmp/hi %S0,%R0" "\n"
"0:"
};
return alt[which_alternative];
}
[(set_attr "length" "8")
(set_attr "type" "arith3")])
@ -1200,9 +1224,19 @@
(ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
(match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
"TARGET_SH2"
"@
cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
cmp/pz\\t%S0"
{
static const char* alt[] =
{
"cmp/eq %S1,%S0" "\n"
" bf{.|/}s 0f" "\n"
" cmp/ge %S1,%S0" "\n"
" cmp/hs %R1,%R0" "\n"
"0:",
"cmp/pz %S0"
};
return alt[which_alternative];
}
[(set_attr "length" "8,2")
(set_attr "type" "arith3,mt_group")])
@ -1215,7 +1249,13 @@
(geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
(match_operand:DI 1 "arith_reg_operand" "r")))]
"TARGET_SH2"
"cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
{
return "cmp/eq %S1,%S0" "\n"
" bf{.|/}s 0f" "\n"
" cmp/hs %S1,%S0" "\n"
" cmp/hs %R1,%R0" "\n"
"0:";
}
[(set_attr "length" "8")
(set_attr "type" "arith3")])
@ -1224,7 +1264,13 @@
(gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
(match_operand:DI 1 "arith_reg_operand" "r")))]
"TARGET_SH2"
"cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
{
return "cmp/eq %S1,%S0" "\n"
" bf{.|/}s 0f" "\n"
" cmp/hi %S1,%S0" "\n"
" cmp/hi %R1,%R0" "\n"
"0:";
}
[(set_attr "length" "8")
(set_attr "type" "arith3")])
@ -1276,7 +1322,7 @@
"cmpgtu %N1, %N2, %0"
[(set_attr "type" "cmp_media")])
; These two patterns are for combine.
; This pattern is for combine.
(define_insn "*cmpne0sisi_media"
[(set (match_operand:SI 0 "register_operand" "=r")
(ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
@ -1527,7 +1573,11 @@
&& (arith_reg_operand (operands[1], SImode)
|| (immediate_operand (operands[1], SImode)
&& satisfies_constraint_I08 (operands[1])))"
"bt 0f\;mov %1,%0\\n0:"
{
return "bt 0f" "\n"
" mov %1,%0" "\n"
"0:";
}
[(set_attr "type" "mt_group,arith") ;; poor approximation
(set_attr "length" "4")])
@ -1540,7 +1590,11 @@
&& (arith_reg_operand (operands[1], SImode)
|| (immediate_operand (operands[1], SImode)
&& satisfies_constraint_I08 (operands[1])))"
"bf 0f\;mov %1,%0\\n0:"
{
return "bf 0f" "\n"
" mov %1,%0" "\n"
"0:";
}
[(set_attr "type" "mt_group,arith") ;; poor approximation
(set_attr "length" "4")])
@ -2581,8 +2635,7 @@
(match_operand:DI 2 "register_operand" "r")]
UNSPEC_DIV_INV_TABLE)))]
"TARGET_SHMEDIA"
"@
ldx.ub %1, %2, %0"
"ldx.ub %1, %2, %0"
[(set_attr "type" "load_media")
(set_attr "highpart" "user")])
@ -2593,8 +2646,7 @@
(match_operand:DI 2 "register_operand" "r")]
UNSPEC_DIV_INV_TABLE)))]
"TARGET_SHMEDIA"
"@
ldx.w %1, %2, %0"
"ldx.w %1, %2, %0"
[(set_attr "type" "load_media")
(set_attr "highpart" "user")])
@ -2924,19 +2976,33 @@ norm32: r25
label:
sub result, round_scratch, result */
int likely = TARGET_DIVIDE_INV20L;
if (! likely) output_asm_insn ("muls.l\t%2, %1 , %8", operands);
output_asm_insn ("muls.l\t%2, %3, %0\;xor\t%12, %5, %7", operands);
output_asm_insn (likely
? "bge/l\t%4, %6, %10\;muls.l\t%2, %1 , %8"
: "bge/u\t%4, %6, %10", operands);
output_asm_insn ("shari\t%8, 16, %8\;muls.l\t%8, %2, %8", operands);
if (! likely) output_asm_insn ("sub\t%0, %7, %0", operands);
output_asm_insn ("shari\t%3, 14, %9\;shari\t%8, 30, %8", operands);
return (likely
? "muls.l\t%8, %9, %8\;sub\t%0, %8, %0\n%11:\tadd\t%0, %7, %0"
: "muls.l\t%8, %9, %7\n%11:\tsub\t%0, %7, %0");
const bool likely = TARGET_DIVIDE_INV20L;
if (likely)
return
"muls.l %2, %3, %0" "\n"
" xor %12, %5, %7" "\n"
" bge/l %4, %6, %10" "\n"
" muls.l %2, %1, %8" "\n"
" shari %8, 16, %8" "\n"
" muls.l %8, %2, %8" "\n"
" shari %3, 14, %9" "\n"
" shari %8, 30, %8" "\n"
" muls.l %8, %9, %8" "\n"
" sub %0, %8, %0" "\n"
"%11: add %0, %7, %0";
else
return
"muls.l %2, %1, %8" "\n"
" muls.l %2, %3, %0" "\n"
" xor %12, %5, %7" "\n"
" bge/u %4, %6, %10" "\n"
" shari %8, 16, %8" "\n"
" muls.l %8, %2, %8" "\n"
" sub %0, %7, %0" "\n"
" shari %3, 14, %9" "\n"
" shari %8, 30, %8" "\n"
" muls.l %8, %9, %7" "\n"
"%11: sub %0, %7, %0";
})
(define_insn_and_split "divsi_inv_fp"
@ -3481,7 +3547,7 @@ label:
(and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
(match_operand:SI 2 "const_int_operand" "Psz")))]
"TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
"bclr\\t%W2,%0"
"bclr %W2,%0"
[(set_attr "type" "arith")])
(define_insn_and_split "anddi3"
@ -3552,7 +3618,7 @@ label:
(ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
(match_operand:SI 2 "const_int_operand" "Pso")))]
"TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
"bset\\t%V2,%0"
"bset %V2,%0"
[(set_attr "type" "arith")])
(define_insn "iordi3"
@ -3672,7 +3738,10 @@ label:
(rotate:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:HI 2 "mextr_bit_offset" "")))]
"TARGET_SHMEDIA"
"if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
{
if (! mextr_bit_offset (operands[2], HImode))
FAIL;
})
(define_insn "rotldi3_mextr"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
@ -3681,8 +3750,7 @@ label:
"TARGET_SHMEDIA"
{
static char templ[16];
sprintf (templ, "mextr%d\\t%%1,%%1,%%0",
sprintf (templ, "mextr%d %%1,%%1,%%0",
8 - (int) (INTVAL (operands[2]) >> 3));
return templ;
}
@ -3705,8 +3773,7 @@ label:
"TARGET_SHMEDIA"
{
static char templ[16];
sprintf (templ, "mextr%d\\t%%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3);
sprintf (templ, "mextr%d %%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3);
return templ;
}
[(set_attr "type" "arith_media")])
@ -4900,9 +4967,19 @@ label:
(match_operand:SI 1 "arith_reg_operand" "0,0")
(neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
"TARGET_SH1 && TARGET_ZDCBRANCH"
"@
bt\\t0f\;neg\\t%2,%0\\n0:
bf\\t0f\;neg\\t%2,%0\\n0:"
{
static const char* alt[] =
{
"bt 0f" "\n"
" neg %2,%0" "\n"
"0:",
"bf 0f" "\n"
" neg %2,%0" "\n"
"0:"
};
return alt[which_alternative];
}
"TARGET_SH1 && ! TARGET_ZDCBRANCH"
[(const_int 0)]
{
@ -5573,9 +5650,16 @@ label:
[(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
(truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
"TARGET_SHMEDIA"
"@
shlli\\t%1,48,%0\;shlri\\t%0,48,%0
st%M0.w %m0, %1"
{
static const char* alt[] =
{
"shlli %1,48,%0" "\n"
" shlri %0,48,%0",
"st%M0.w %m0, %1"
};
return alt[which_alternative];
}
[(set_attr "type" "arith_media,store_media")
(set_attr "length" "8,4")
(set (attr "highpart")
@ -5888,9 +5972,9 @@ label:
"(TARGET_SH1 || TARGET_SH2E || TARGET_SH2A)
&& ! TARGET_SH3"
"@
mov.l %1,%0
lds.l %1,%0
lds.l %1,%0"
mov.l %1,%0
lds.l %1,%0
lds.l %1,%0"
[(set_attr "type" "load_si,mem_mac,pload")
(set_attr "length" "2,2,2")
(set_attr "in_delay_slot" "no,no,no")])
@ -6192,7 +6276,12 @@ label:
UNSPEC_ICACHE)
(clobber (match_scratch:SI 2 "=&r"))]
"TARGET_HARD_SH4"
"ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
{
return "ocbwb @%0" "\n"
" extu.w %0,%2" "\n"
" or %1,%2" "\n"
" mov.l %0,@%2";
}
[(set_attr "length" "8")
(set_attr "type" "cwb")])
@ -6200,8 +6289,12 @@ label:
[(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
UNSPEC_ICACHE)]
"TARGET_SH4A_ARCH || TARGET_SH4_300"
"ocbwb\\t@%0\;synco\;icbi\\t@%0"
[(set_attr "length" "16")
{
return "ocbwb @%0" "\n"
" synco" "\n"
" icbi @%0";
}
[(set_attr "length" "16") ;; FIXME: Why 16 and not 6? Looks like typo.
(set_attr "type" "cwb")])
;; ??? could make arg 0 an offsettable memory operand to allow to save
@ -6210,7 +6303,12 @@ label:
[(unspec_volatile [(match_operand 0 "any_register_operand" "r")]
UNSPEC_ICACHE)]
"TARGET_SHMEDIA"
"ocbwb %0,0\;synco\;icbi %0, 0\;synci"
{
return "ocbwb %0,0" "\n"
" synco" "\n"
" icbi %0,0" "\n"
" synci";
}
[(set_attr "length" "16")
(set_attr "type" "invalidate_line_media")])
@ -6934,9 +7032,11 @@ label:
if (TARGET_FMOVD)
return "fmov %1,%0";
else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
return "fmov %R1,%R0\n\tfmov %S1,%S0";
return "fmov %R1,%R0" "\n"
" fmov %S1,%S0";
else
return "fmov %S1,%S0\n\tfmov %R1,%R0";
return "fmov %S1,%S0" "\n"
" fmov %R1,%R0";
case 3:
case 4:
return "fmov.d %1,%0";
@ -8199,9 +8299,9 @@ label:
"TARGET_SH1"
{
if (TARGET_SH2A && (dbr_sequence_length () == 0))
return "jsr/n\\t@%0";
return "jsr/n @%0";
else
return "jsr\\t@%0%#";
return "jsr @%0%#";
}
[(set_attr "type" "call")
(set (attr "fp_mode")
@ -8225,7 +8325,7 @@ label:
vect_num = sh2a_get_function_vector_number (operands[0]);
operands[2] = GEN_INT (vect_num * 4);
return "jsr/n\\t@@(%O2,tbr)";
return "jsr/n @@(%O2,tbr)";
}
[(set_attr "type" "call")
(set (attr "fp_mode")
@ -8244,7 +8344,10 @@ label:
(use (match_operand 2 "" ""))
(clobber (reg:SI PR_REG))]
"TARGET_SH2"
"bsrf %0\\n%O2:%#"
{
return "bsrf %0" "\n"
"%O2:%#";
}
[(set_attr "type" "call")
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
@ -8330,9 +8433,9 @@ label:
"TARGET_SH1"
{
if (TARGET_SH2A && (dbr_sequence_length () == 0))
return "jsr/n\\t@%1";
return "jsr/n @%1";
else
return "jsr\\t@%1%#";
return "jsr @%1%#";
}
[(set_attr "type" "call")
(set (attr "fp_mode")
@ -8357,7 +8460,7 @@ label:
vect_num = sh2a_get_function_vector_number (operands[1]);
operands[3] = GEN_INT (vect_num * 4);
return "jsr/n\\t@@(%O3,tbr)";
return "jsr/n @@(%O3,tbr)";
}
[(set_attr "type" "call")
(set (attr "fp_mode")
@ -8375,7 +8478,10 @@ label:
(use (match_operand 3 "" ""))
(clobber (reg:SI PR_REG))]
"TARGET_SH2"
"bsrf %1\\n%O3:%#"
{
return "bsrf %1" "\n"
"%O3:%#";
}
[(set_attr "type" "call")
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
@ -8761,7 +8867,10 @@ label:
(use (reg:PSI FPSCR_REG))
(return)]
"TARGET_SH2"
"braf %0\\n%O2:%#"
{
return "braf %0" "\n"
"%O2:%#";
}
[(set_attr "needs_delay_slot" "yes")
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
@ -8821,9 +8930,16 @@ label:
;; because sibcall_epilogue may clobber MACL_REG.
(clobber (reg:SI MACL_REG))]
"TARGET_SHCOMPACT"
"@
jmp @%0%#
jmp @%0\\n sts %2, r0"
{
static const char* alt[] =
{
"jmp @%0%#",
"jmp @%0" "\n"
" sts %2,r0"
};
return alt[which_alternative];
}
[(set_attr "needs_delay_slot" "yes,no")
(set_attr "length" "2,4")
(set (attr "fp_mode") (const_string "single"))
@ -8958,7 +9074,10 @@ label:
(use (reg:PSI FPSCR_REG))
(return)]
"TARGET_SH2"
"braf %1\\n%O3:%#"
{
return "braf %1" "\n"
"%O3:%#";
}
[(set_attr "needs_delay_slot" "yes")
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
@ -9006,9 +9125,16 @@ label:
;; because sibcall_epilogue may clobber MACL_REG.
(clobber (reg:SI MACL_REG))]
"TARGET_SHCOMPACT"
"@
jmp @%1%#
jmp @%1\\n sts %3, r0"
{
static const char* alt[] =
{
"jmp @%1%#",
"jmp @%1" "\n"
" sts %3,r0"
};
return alt[which_alternative];
}
[(set_attr "needs_delay_slot" "yes,no")
(set_attr "length" "2,4")
(set (attr "fp_mode") (const_string "single"))
@ -9932,13 +10058,18 @@ label:
switch (GET_MODE (diff_vec))
{
case SImode:
return "shll2 %1\;mov.l @(r0,%1),%0";
return "shll2 %1" "\n"
" mov.l @(r0,%1),%0";
case HImode:
return "add %1,%1\;mov.w @(r0,%1),%0";
return "add %1,%1" "\n"
" mov.w @(r0,%1),%0";
case QImode:
if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
return "mov.b @(r0,%1),%0\;extu.b %0,%0";
return "mov.b @(r0,%1),%0";
return "mov.b @(r0,%1),%0" "\n"
" extu.b %0,%0";
else
return "mov.b @(r0,%1),%0";
default:
gcc_unreachable ();
}
@ -9955,29 +10086,33 @@ label:
"TARGET_SH2 && reload_completed && flag_pic"
{
rtx diff_vec = PATTERN (next_real_insn (operands[2]));
const char *load;
gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
switch (GET_MODE (diff_vec))
{
case SImode:
output_asm_insn ("shll2 %1", operands);
load = "mov.l @(r0,%1),%0"; break;
return "shll2 %1" "\n"
" add r0,%1" "\n"
" mova %O3,r0" "\n"
" mov.l @(r0,%1),%0";
case HImode:
output_asm_insn ("add %1,%1", operands);
load = "mov.w @(r0,%1),%0"; break;
return "add %1,%1" "\n"
" add r0,%1" "\n"
" mova %O3,r0" "\n"
" mov.w @(r0,%1),%0";
case QImode:
if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
load = "mov.b @(r0,%1),%0\;extu.b %0,%0";
return "add r0,%1" "\n"
" mova %O3,r0" "\n"
" mov.b @(r0,%1),%0" "\n"
" extu.b %0,%0";
else
load = "mov.b @(r0,%1),%0";
break;
return "add r0,%1" "\n"
" mova %O3,r0" "\n"
" mov.b @(r0,%1),%0";
default:
gcc_unreachable ();
}
output_asm_insn ("add\tr0,%1\;mova\t%O3,r0\\n", operands);
return load;
}
[(set_attr "length" "8")])
@ -10261,7 +10396,7 @@ label:
(set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
(set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
"TARGET_SH2A && REGNO (operands[0]) == 15"
"movml.l\tr7,@-r15"
"movml.l r7,@-r15"
[(set_attr "in_delay_slot" "no")])
(define_insn "movml_pop_banked"
@ -10276,7 +10411,7 @@ label:
(set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
(set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
"TARGET_SH2A && REGNO (operands[0]) == 15"
"movml.l\t@r15+,r7"
"movml.l @r15+,r7"
[(set_attr "in_delay_slot" "no")])
;; ------------------------------------------------------------------------
@ -12194,8 +12329,8 @@ label:
(match_dup 0)))]
"TARGET_SH2A && TARGET_BITOPS"
"@
bclr.b\\t%1,%0
bclr.b\\t%1,@(0,%t0)"
bclr.b %1,%0
bclr.b %1,@(0,%t0)"
[(set_attr "length" "4,4")])
(define_insn "bclrmem_m2a"
@ -12204,8 +12339,8 @@ label:
(match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
"TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
"@
bclr.b\\t%W1,%0
bclr.b\\t%W1,@(0,%t0)"
bclr.b %W1,%0
bclr.b %W1,@(0,%t0)"
[(set_attr "length" "4,4")])
;; Set a bit in a memory location.
@ -12217,8 +12352,8 @@ label:
(match_dup 0)))]
"TARGET_SH2A && TARGET_BITOPS"
"@
bset.b\\t%1,%0
bset.b\\t%1,@(0,%t0)"
bset.b %1,%0
bset.b %1,@(0,%t0)"
[(set_attr "length" "4,4")])
(define_insn "bsetmem_m2a"
@ -12227,8 +12362,8 @@ label:
(match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
"TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
"@
bset.b\\t%V1,%0
bset.b\\t%V1,@(0,%t0)"
bset.b %V1,%0
bset.b %V1,@(0,%t0)"
[(set_attr "length" "4,4")])
;;; Transfer the contents of the T bit to a specified bit of memory.
@ -12244,8 +12379,8 @@ label:
(match_dup 0))))]
"TARGET_SH2A && TARGET_BITOPS"
"@
bst.b\\t%1,%0
bst.b\\t%1,@(0,%t0)"
bst.b %1,%0
bst.b %1,@(0,%t0)"
[(set_attr "length" "4")])
;; Store a specified bit of memory in the T bit.
@ -12257,8 +12392,8 @@ label:
(match_operand 1 "const_int_operand" "K03,K03")))]
"TARGET_SH2A && TARGET_BITOPS"
"@
bld.b\\t%1,%0
bld.b\\t%1,@(0,%t0)"
bld.b %1,%0
bld.b %1,@(0,%t0)"
[(set_attr "length" "4,4")])
;; Store a specified bit of memory in the T bit.
@ -12270,8 +12405,8 @@ label:
(match_operand 1 "const_int_operand" "K03,K03")))]
"TARGET_SH2A && TARGET_BITOPS"
"@
bld.b\\t%1,%0
bld.b\\t%1,@(0,%t0)"
bld.b %1,%0
bld.b %1,@(0,%t0)"
[(set_attr "length" "4,4")])
;; Store a specified bit of the LSB 8 bits of a register in the T bit.
@ -12281,7 +12416,7 @@ label:
(const_int 1)
(match_operand 1 "const_int_operand" "K03")))]
"TARGET_SH2A"
"bld\\t%1,%0")
"bld %1,%0")
(define_insn "*bld_regqi"
[(set (reg:SI T_REG)
@ -12289,7 +12424,7 @@ label:
(const_int 1)
(match_operand 1 "const_int_operand" "K03")))]
"TARGET_SH2A"
"bld\\t%1,%0")
"bld %1,%0")
;; Take logical and of a specified bit of memory with the T bit and
;; store its result in the T bit.
@ -12302,8 +12437,8 @@ label:
(match_operand 1 "const_int_operand" "K03,K03"))))]
"TARGET_SH2A && TARGET_BITOPS"
"@
band.b\\t%1,%0
band.b\\t%1,@(0,%t0)"
band.b %1,%0
band.b %1,@(0,%t0)"
[(set_attr "length" "4,4")])
(define_insn "bandreg_m2a"
@ -12314,9 +12449,17 @@ label:
(match_operand 2 "const_int_operand" "K03,K03"))
(match_operand:SI 3 "register_operand" "r,r")))]
"TARGET_SH2A && TARGET_BITOPS"
"@
band.b\\t%2,%1\;movt\\t%0
band.b\\t%2,@(0,%t1)\;movt\\t%0"
{
static const char* alt[] =
{
"band.b %2,%1" "\n"
" movt %0",
"band.b %2,@(0,%t1)" "\n"
" movt %0"
};
return alt[which_alternative];
}
[(set_attr "length" "6,6")])
;; Take logical or of a specified bit of memory with the T bit and
@ -12330,8 +12473,8 @@ label:
(match_operand 1 "const_int_operand" "K03,K03"))))]
"TARGET_SH2A && TARGET_BITOPS"
"@
bor.b\\t%1,%0
bor.b\\t%1,@(0,%t0)"
bor.b %1,%0
bor.b %1,@(0,%t0)"
[(set_attr "length" "4,4")])
(define_insn "borreg_m2a"
@ -12342,9 +12485,17 @@ label:
(match_operand 2 "const_int_operand" "K03,K03"))
(match_operand:SI 3 "register_operand" "=r,r")))]
"TARGET_SH2A && TARGET_BITOPS"
"@
bor.b\\t%2,%1\;movt\\t%0
bor.b\\t%2,@(0,%t1)\;movt\\t%0"
{
static const char* alt[] =
{
"bor.b %2,%1" "\n"
" movt %0",
"bor.b %2,@(0,%t1)" "\n"
" movt %0"
};
return alt[which_alternative];
}
[(set_attr "length" "6,6")])
;; Take exclusive or of a specified bit of memory with the T bit and
@ -12358,8 +12509,8 @@ label:
(match_operand 1 "const_int_operand" "K03,K03"))))]
"TARGET_SH2A && TARGET_BITOPS"
"@
bxor.b\\t%1,%0
bxor.b\\t%1,@(0,%t0)"
bxor.b %1,%0
bxor.b %1,@(0,%t0)"
[(set_attr "length" "4,4")])
(define_insn "bxorreg_m2a"
@ -12370,9 +12521,17 @@ label:
(match_operand 2 "const_int_operand" "K03,K03"))
(match_operand:SI 3 "register_operand" "=r,r")))]
"TARGET_SH2A && TARGET_BITOPS"
"@
bxor.b\\t%2,%1\;movt\\t%0
bxor.b\\t%2,@(0,%t1)\;movt\\t%0"
{
static const char* alt[] =
{
"bxor.b %2,%1" "\n"
" movt %0",
"bxor.b %2,@(0,%t1)" "\n"
" movt %0"
};
return alt[which_alternative];
}
[(set_attr "length" "6,6")])
@ -12607,23 +12766,28 @@ label:
&& reg_unused_after (operands[0], insn)"
"fmov{.s|} @(%0,%1),%2")
;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
(define_insn "sp_switch_1"
[(const_int 1) (match_operand:SI 0 "symbol_ref_operand" "s")]
"TARGET_SH1"
{
output_asm_insn ("mov.l r0,@-r15\;mov.l %0,r0", operands);
output_asm_insn ("mov.l @r0,r0\;mov.l r15,@-r0", operands);
return "mov r0,r15";
return "mov.l r0,@-r15" "\n"
" mov.l %0,r0" "\n"
" mov.l @r0,r0" "\n"
" mov.l r15,@-r0" "\n"
" mov r0,r15";
}
[(set_attr "length" "10")])
;; Switch back to the original stack for interrupt functions with the
;; sp_switch attribute. */
;; sp_switch attribute.
(define_insn "sp_switch_2"
[(const_int 2)]
"TARGET_SH1"
"mov.l @r15+,r15\;mov.l @r15+,r0"
{
return "mov.l @r15+,r15" "\n"
" mov.l @r15+,r0";
}
[(set_attr "length" "4")])
;; Integer vector moves
@ -12980,7 +13144,8 @@ label:
"TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
{
static char templ[21];
sprintf (templ, "mextr%d\\t%%N1, %%N2, %%0", (int) INTVAL (operands[3]) >> 3);
sprintf (templ, "mextr%d %%N1, %%N2, %%0",
(int) INTVAL (operands[3]) >> 3);
return templ;
}
[(set_attr "type" "arith_media")])
@ -12994,7 +13159,8 @@ label:
"TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
{
static char templ[21];
sprintf (templ, "mextr%d\\t%%N2, %%N1, %%0", (int) INTVAL (operands[4]) >> 3);
sprintf (templ, "mextr%d %%N2, %%N1, %%0",
(int) INTVAL (operands[4]) >> 3);
return templ;
}
[(set_attr "type" "arith_media")])
@ -14505,7 +14671,11 @@ label:
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
(set (match_scratch:SI 2 "=&r") (const_int 0))]
"!TARGET_SHMEDIA"
"mov.l\t%1, %2\;mov.l\t%2, %0\;mov\t#0, %2"
{
return "mov.l %1,%2" "\n"
" mov.l %2,%0" "\n"
" mov #0,%2";
}
[(set_attr "type" "other")
(set_attr "length" "6")])
@ -14514,7 +14684,11 @@ label:
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
(set (match_scratch:SI 2 "=&r") (const_int 0))]
"TARGET_SHMEDIA"
"ld%M1.l\t%m1, %2\;st%M0.l\t%m0, %2\;movi\t0, %2"
{
return "ld%M1.l %m1,%2" "\n"
" st%M0.l %m0,%2" "\n"
" movi 0,%2";
}
[(set_attr "type" "other")
(set_attr "length" "12")])
@ -14523,7 +14697,11 @@ label:
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
(set (match_scratch:DI 2 "=&r") (const_int 0))]
"TARGET_SHMEDIA64"
"ld%M1.q\t%m1, %2\;st%M0.q\t%m0, %2\;movi\t0, %2"
{
return "ld%M1.q %m1,%2" "\n"
" st%M0.q %m0,%2" "\n"
" movi 0,%2";
}
[(set_attr "type" "other")
(set_attr "length" "12")])
@ -14569,7 +14747,13 @@ label:
(set (match_scratch:SI 2 "=&r") (const_int 0))
(set (match_scratch:SI 3 "=&r") (const_int 0))]
"!TARGET_SHMEDIA"
"mov.l\t%0, %2\;mov.l\t%1, %3\;cmp/eq\t%2, %3\;mov\t#0, %2\;mov\t#0, %3"
{
return "mov.l %0,%2" "\n"
" mov.l %1,%3" "\n"
" cmp/eq %2,%3" "\n"
" mov #0,%2" "\n"
" mov #0,%3";
}
[(set_attr "type" "other")
(set_attr "length" "10")])
@ -14580,7 +14764,12 @@ label:
UNSPEC_SP_TEST))
(set (match_scratch:SI 3 "=&r") (const_int 0))]
"TARGET_SHMEDIA"
"ld%M1.l\t%m1, %0\;ld%M2.l\t%m2, %3\;cmpeq\t%0, %3, %0\;movi\t0, %3"
{
return "ld%M1.l %m1,%0" "\n"
" ld%M2.l %m2,%3" "\n"
" cmpeq %0,%3,%0" "\n"
" movi 0,%3";
}
[(set_attr "type" "other")
(set_attr "length" "16")])
@ -14591,7 +14780,12 @@ label:
UNSPEC_SP_TEST))
(set (match_scratch:DI 3 "=&r") (const_int 0))]
"TARGET_SHMEDIA64"
"ld%M1.q\t%m1, %0\;ld%M2.q\t%m2, %3\;cmpeq\t%0, %3, %0\;movi\t0, %3"
{
return "ld%M1.q %m1,%0" "\n"
" ld%M2.q %m2,%3" "\n"
" cmpeq %0,%3,%0" "\n"
" movi 0,%3";
}
[(set_attr "type" "other")
(set_attr "length" "16")])