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re PR middle-end/37286 (gfortran, trunk: ICE subst_stack_regs_pat, at reg-stack.c:1537)

Browse source 
PR middle-end/37286
	* reg-stack.c (subst_stack_regs_pat) [MINUS, DIV, MULT, PLUS]:
	Initialize uninitialized input registers with a NaN.

testsuite/ChangeLog:

	PR middle-end/37286
	* gfortran.dg/pr37286.f90: New test.

From-SVN: r141603
This commit is contained in:
Uros Bizjak 2008-11-05 10:57:49 +01:00
parent 8e66def0a1
commit 34e4536eaf
4 changed files with 134 additions and 50 deletions
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49
gcc/ChangeLog
View file

@ -1,3 +1,9 @@
2008-11-05 Uros Bizjak <ubizjak@gmail.com>
PR middle-end/37286
* reg-stack.c (subst_stack_regs_pat) [MINUS, DIV, MULT, PLUS]:
Initialize uninitialized input registers with a NaN.
2008-11-05 Tobias Grosser <grosser@fim.uni-passau.de> 2008-11-05 Tobias Grosser <grosser@fim.uni-passau.de>
PR middle-end/37833 PR middle-end/37833
@ -38,7 +44,7 @@
2008-11-03 Mikael Pettersson <mikpe@it.uu.se> 2008-11-03 Mikael Pettersson <mikpe@it.uu.se>
PR target/37989 PR target/37989
* config/i386/mingw32.h (REAL_LIBGCC_SPEC): Only add libgcc_s.a * config/i386/mingw32.h (REAL_LIBGCC_SPEC): Only add libgcc_s.a
or libgcc_eh.a to spec if ENABLE_SHARED_LIBGCC. or libgcc_eh.a to spec if ENABLE_SHARED_LIBGCC.
@ -47,7 +53,7 @@
* config/mips.c (mips_conditional_register_usage): Handle the * config/mips.c (mips_conditional_register_usage): Handle the
DSP control register. DSP control register.
* doc/extend.texi: Document the DSP control register. * doc/extend.texi: Document the DSP control register.
2008-11-03 Steve Ellcey <sje@cup.hp.com> 2008-11-03 Steve Ellcey <sje@cup.hp.com>
Jakub Jelinek <jakub@redhat.com> Jakub Jelinek <jakub@redhat.com>
@ -404,16 +410,14 @@
2008-10-27 Vladimir Makarov <vmakarov@redhat.com> 2008-10-27 Vladimir Makarov <vmakarov@redhat.com>
PR middle-end/37813 PR middle-end/37813
* ira-conflicts.c (process_regs_for_copy): Remove class subset * ira-conflicts.c (process_regs_for_copy): Remove class subset check.
check.
* ira-int.h (ira_hard_regno_cover_class): New. * ira-int.h (ira_hard_regno_cover_class): New.
* ira-lives.c (mark_reg_live, mark_reg_dead, * ira-lives.c (mark_reg_live, mark_reg_dead,
process_bb_node_lives): Use ira_hard_regno_cover_class. process_bb_node_lives): Use ira_hard_regno_cover_class.
* ira.c (reg_class ira_hard_regno_cover_class): New global * ira.c (reg_class ira_hard_regno_cover_class): New global variable.
variable.
(setup_hard_regno_cover_class): New function. (setup_hard_regno_cover_class): New function.
(ira_init): Call setup_hard_regno_cover_class. (ira_init): Call setup_hard_regno_cover_class.
@ -431,8 +435,8 @@
2008-10-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2008-10-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
PR middle-end/37316 PR middle-end/37316
* pa.c (function_arg_padding): Pad complex and vector types upward in * pa.c (function_arg_padding): Pad complex and vector types
64-bit runtime. upward in 64-bit runtime.
(function_arg): Use BLKmode for PARALLEL in 64-bit runtime. (function_arg): Use BLKmode for PARALLEL in 64-bit runtime.
2008-10-26 Matthias Klose <doko@ubuntu.com> 2008-10-26 Matthias Klose <doko@ubuntu.com>
@ -453,8 +457,7 @@
* doc/tm.texi (FUNCTION_ARG_OFFSET): Document new macro. * doc/tm.texi (FUNCTION_ARG_OFFSET): Document new macro.
* config/spu/spu.h (FUNCTION_ARG_OFFSET): New macro to move char * config/spu/spu.h (FUNCTION_ARG_OFFSET): New macro to move char
and short arguments to the correct location as mandated by the and short arguments to the correct location as mandated by the ABI.
ABI.
2008-10-24 Kaz Kojima <kkojima@gcc.gnu.org> 2008-10-24 Kaz Kojima <kkojima@gcc.gnu.org>
@ -500,8 +503,7 @@
check_p_tool, check_p_vars, check_p_subno, check_p_comma, check_p_tool, check_p_vars, check_p_subno, check_p_comma,
check_p_subwork, check_p_numbers, check_p_subdir, check_p_subdirs): check_p_subwork, check_p_numbers, check_p_subdir, check_p_subdirs):
New variables. New variables.
(check-subtargets, check-%-subtargets, check-parallel-%): New (check-subtargets, check-%-subtargets, check-parallel-%): New targets.
targets.
(check-%): For test targets listed in lang_checks_parallelized (check-%): For test targets listed in lang_checks_parallelized
if -j is used and RUNTESTFLAGS doesn't specify tests to execute, if -j is used and RUNTESTFLAGS doesn't specify tests to execute,
run the testing in multiple make goals, possibly parallel, and run the testing in multiple make goals, possibly parallel, and
@ -740,8 +742,7 @@
2008-10-15 Jan Hubicka <jh@suse.cz> 2008-10-15 Jan Hubicka <jh@suse.cz>
* ira-emit.c (change_regs): Return false when replacing reg by * ira-emit.c (change_regs): Return false when replacing reg by itself.
itself.
2008-10-14 Vladimir Makarov <vmakarov@redhat.com> 2008-10-14 Vladimir Makarov <vmakarov@redhat.com>
@ -942,8 +943,8 @@
Define new target hooks. Define new target hooks.
(TARGET_SCHED_GEN_CHECK): Rename to TARGET_SCHED_GEN_SPEC_CHECK. (TARGET_SCHED_GEN_CHECK): Rename to TARGET_SCHED_GEN_SPEC_CHECK.
(ia64_optimization_options): Turn on selective scheduling with -O3, (ia64_optimization_options): Turn on selective scheduling with -O3,
disable -fauto-inc-dec. Set mflag_sched_control_spec to true by default disable -fauto-inc-dec. Set mflag_sched_control_spec to true by
with selective scheduling. default with selective scheduling.
(ia64_override_options): Initialize align_loops and align_functions (ia64_override_options): Initialize align_loops and align_functions
to 32 and 64, respectively. Set global selective scheduling flags to 32 and 64, respectively. Set global selective scheduling flags
according to target-dependent flags. according to target-dependent flags.
@ -1005,8 +1006,8 @@
(final_emit_insn_group_barriers): Emit stop bits before insns starting (final_emit_insn_group_barriers): Emit stop bits before insns starting
a new cycle. a new cycle.
(sel2_run): New variable. (sel2_run): New variable.
(ia64_reorg): When flag_selective_scheduling2 is set, run the selective (ia64_reorg): When flag_selective_scheduling2 is set, run the
scheduling pass instead of schedule_ebbs. selective scheduling pass instead of schedule_ebbs.
* config/ia64/ia64.md (speculable1, speculable2): New attributes. * config/ia64/ia64.md (speculable1, speculable2): New attributes.
(UNSPEC_LDS_A): New UNSPEC. (UNSPEC_LDS_A): New UNSPEC.
@ -1077,8 +1078,8 @@
* config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Define. * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Define.
* config/rs6000/rs6000.md * config/rs6000/rs6000.md
Replace cc_reg_not_cr0_operand with cc_reg_not_micro_cr0_operand if Replace cc_reg_not_cr0_operand with cc_reg_not_micro_cr0_operand if
the instruction would have been microcoded on the Cell. Set cell_micro the instruction would have been microcoded on the Cell. Set
to always on unnamed patterns for the string instructions. cell_micro to always on unnamed patterns for the string instructions.
(cell_micro): Update definition, remove load/store conditional (cell_micro): Update definition, remove load/store conditional
microcoded. microcoded.
(sign_extend:DI): Define new pattern for non microcoded version. (sign_extend:DI): Define new pattern for non microcoded version.
@ -1380,8 +1381,8 @@
* pa.md (call, call_value): Generate an rtx for register r4 and pass * pa.md (call, call_value): Generate an rtx for register r4 and pass
it to PIC call patterns. it to PIC call patterns.
(call_symref_pic): Revise pattern to expose PIC register save. Remove (call_symref_pic): Revise pattern to expose PIC register save. Remove
code generation and attributes from pattern. Change peephole2 to split code generation and attributes from pattern. Change peephole2 to
for noreturn case. Revise split pattern for non noreturn case. split for noreturn case. Revise split pattern for non noreturn case.
(call_symref_64bit, call_reg_pic, call_reg_64bit, call_val_symref_pic, (call_symref_64bit, call_reg_pic, call_reg_64bit, call_val_symref_pic,
call_val_symref_64bit, call_val_reg_pic, call_val_reg_64bit): Likewise. call_val_symref_64bit, call_val_reg_pic, call_val_reg_64bit): Likewise.
* pa.c (attr_length_call): Simplify extraction of call rtx. Add some * pa.c (attr_length_call): Simplify extraction of call rtx. Add some
@ -1507,8 +1508,8 @@
* tree.h (get_object_alignment): Declare. * tree.h (get_object_alignment): Declare.
* emit-rtl.c (set_mem_attributes_minus_bitpos): Call * emit-rtl.c (set_mem_attributes_minus_bitpos): Call
get_object_alignment if needed. get_object_alignment if needed.
* builtins.c (get_pointer_alignment): Move ADDR_EXPR operand handling * builtins.c (get_pointer_alignment): Move ADDR_EXPR operand
to ... handling to ...
(get_object_alignment): ... here. New function. Try harder to (get_object_alignment): ... here. New function. Try harder to
determine alignment from get_inner_reference returned offset. determine alignment from get_inner_reference returned offset.

23
gcc/reg-stack.c
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@ -1527,15 +1527,30 @@ subst_stack_regs_pat (rtx insn, stack regstack, rtx pat)
else else
{ {
/* Both operands are REG. If neither operand is already /* Both operands are REG. If neither operand is already
at the top of stack, choose to make the one that is the dest at the top of stack, choose to make the one that is the
the new top of stack. */ dest the new top of stack. */
int src1_hard_regnum, src2_hard_regnum; int src1_hard_regnum, src2_hard_regnum;
src1_hard_regnum = get_hard_regnum (regstack, *src1); src1_hard_regnum = get_hard_regnum (regstack, *src1);
src2_hard_regnum = get_hard_regnum (regstack, *src2); src2_hard_regnum = get_hard_regnum (regstack, *src2);
gcc_assert (src1_hard_regnum != -1);
gcc_assert (src2_hard_regnum != -1); /* If the source is not live, this is yet another case of
uninitialized variables. Load up a NaN instead. */
if (src1_hard_regnum == -1)
{
rtx pat2 = gen_rtx_CLOBBER (VOIDmode, *src1);
rtx insn2 = emit_insn_before (pat2, insn);
control_flow_insn_deleted
|= move_nan_for_stack_reg (insn2, regstack, *src1);
}
if (src2_hard_regnum == -1)
{
rtx pat2 = gen_rtx_CLOBBER (VOIDmode, *src2);
rtx insn2 = emit_insn_before (pat2, insn);
control_flow_insn_deleted
|= move_nan_for_stack_reg (insn2, regstack, *src2);
}
if (src1_hard_regnum != FIRST_STACK_REG if (src1_hard_regnum != FIRST_STACK_REG
&& src2_hard_regnum != FIRST_STACK_REG) && src2_hard_regnum != FIRST_STACK_REG)

54
gcc/testsuite/ChangeLog
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@ -1,7 +1,12 @@
2008-11-05 Uros Bizjak <ubizjak@gmail.com>
PR middle-end/37286
* gfortran.dg/pr37286.f90: New test.
2008-11-04 Paul Thomas <pault@gcc.gnu.org> 2008-11-04 Paul Thomas <pault@gcc.gnu.org>
PR fortran/37597 PR fortran/37597
* gfortran.dg/host_assoc_call_5.f90: New test. * gfortran.dg/host_assoc_call_5.f90: New test.
2008-11-04 Jakub Jelinek <jakub@redhat.com> 2008-11-04 Jakub Jelinek <jakub@redhat.com>
Andrew Pinski <andrew_pinski@playstation.sony.com> Andrew Pinski <andrew_pinski@playstation.sony.com>
@ -274,22 +279,22 @@
* gcc.target/bfin/hisilh-O0.c: New file. * gcc.target/bfin/hisilh-O0.c: New file.
From Mike Frysinger <michael.frysinger@analog.com> From Mike Frysinger <michael.frysinger@analog.com>
* gcc.target/bfin/mcpu-bf522.c: Check SILICON_REVISION is 0x0002. Invert * gcc.target/bfin/mcpu-bf522.c: Check SILICON_REVISION is 0x0002.
check for __WORKAROUND_RETS when SILICON_REVISION is 0x0002+. Invert check for __WORKAROUND_RETS when SILICON_REVISION is 0x0002+.
* gcc.target/bfin/mcpu-bf523.c: Likewise. * gcc.target/bfin/mcpu-bf523.c: Likewise.
* gcc.target/bfin/mcpu-bf524.c: Likewise. * gcc.target/bfin/mcpu-bf524.c: Likewise.
* gcc.target/bfin/mcpu-bf525.c: Likewise. * gcc.target/bfin/mcpu-bf525.c: Likewise.
* gcc.target/bfin/mcpu-bf526.c: Likewise. * gcc.target/bfin/mcpu-bf526.c: Likewise.
* gcc.target/bfin/mcpu-bf527.c: Likewise. * gcc.target/bfin/mcpu-bf527.c: Likewise.
* gcc.target/bfin/mcpu-bf531.c: Check SILICON_REVISION is 0x0006. Invert * gcc.target/bfin/mcpu-bf531.c: Check SILICON_REVISION is 0x0006.
check for __WORKAROUND_RETS when SILICON_REVISION is 0x0006+. Invert check for __WORKAROUND_RETS when SILICON_REVISION is 0x0006+.
* gcc.target/bfin/mcpu-bf532.c: Likewise. * gcc.target/bfin/mcpu-bf532.c: Likewise.
* gcc.target/bfin/mcpu-bf533.c: Likewise. * gcc.target/bfin/mcpu-bf533.c: Likewise.
* gcc.target/bfin/mcpu-bf538.c: Check SILICON_REVISION is 0x0005. Invert * gcc.target/bfin/mcpu-bf538.c: Check SILICON_REVISION is 0x0005.
check for __WORKAROUND_RETS when SILICON_REVISION is 0x0005+. Invert check for __WORKAROUND_RETS when SILICON_REVISION is 0x0005+.
* gcc.target/bfin/mcpu-bf539.c: Likewise. * gcc.target/bfin/mcpu-bf539.c: Likewise.
* gcc.target/bfin/mcpu-bf542.c: Check SILICON_REVISION is 0x0002. Invert * gcc.target/bfin/mcpu-bf542.c: Check SILICON_REVISION is 0x0002.
check for __WORKAROUND_RETS when SILICON_REVISION is 0x0002+. Invert check for __WORKAROUND_RETS when SILICON_REVISION is 0x0002+.
* gcc.target/bfin/mcpu-bf544.c: Likewise. * gcc.target/bfin/mcpu-bf544.c: Likewise.
* gcc.target/bfin/mcpu-bf547.c: Likewise. * gcc.target/bfin/mcpu-bf547.c: Likewise.
* gcc.target/bfin/mcpu-bf548.c: Likewise. * gcc.target/bfin/mcpu-bf548.c: Likewise.
@ -3192,8 +3197,8 @@
2008-08-24 Daniel Kraft <d@domob.eu> 2008-08-24 Daniel Kraft <d@domob.eu>
* gfortran.dg/finalize_5.f03: Adapted expected error message to changes * gfortran.dg/finalize_5.f03: Adapted expected error message to
to handling of CONTAINS in derived-type declarations. changes to handling of CONTAINS in derived-type declarations.
* gfortran.dg/typebound_proc_1.f08: New test. * gfortran.dg/typebound_proc_1.f08: New test.
* gfortran.dg/typebound_proc_2.f90: New test. * gfortran.dg/typebound_proc_2.f90: New test.
* gfortran.dg/typebound_proc_3.f03: New test. * gfortran.dg/typebound_proc_3.f03: New test.
@ -7000,11 +7005,16 @@
2008-05-08 Rafael Espíndola <espindola@google.com> 2008-05-08 Rafael Espíndola <espindola@google.com>
* gcc.dg/vect/vect-111.c: Rename to no-trapping-math-vect-111.c * gcc.dg/vect/vect-111.c: Rename to no-trapping-math-vect-111.c
* gcc.dg/vect/vect-ifcvt-11.c: Rename to no-trapping-math-vect-ifcvt-11.c * gcc.dg/vect/vect-ifcvt-11.c: Rename to
* gcc.dg/vect/vect-ifcvt-12.c: Rename to no-trapping-math-vect-ifcvt-12.c no-trapping-math-vect-ifcvt-11.c
* gcc.dg/vect/vect-ifcvt-13.c: Rename to no-trapping-math-vect-ifcvt-13.c * gcc.dg/vect/vect-ifcvt-12.c: Rename to
* gcc.dg/vect/vect-ifcvt-14.c: Rename to no-trapping-math-vect-ifcvt-14.c no-trapping-math-vect-ifcvt-12.c
* gcc.dg/vect/vect-ifcvt-15.c: Rename to no-trapping-math-vect-ifcvt-15.c * gcc.dg/vect/vect-ifcvt-13.c: Rename to
no-trapping-math-vect-ifcvt-13.c
* gcc.dg/vect/vect-ifcvt-14.c: Rename to
no-trapping-math-vect-ifcvt-14.c
* gcc.dg/vect/vect-ifcvt-15.c: Rename to
no-trapping-math-vect-ifcvt-15.c
2008-05-08 David Daney <ddaney@avtrex.com> 2008-05-08 David Daney <ddaney@avtrex.com>
@ -9083,8 +9093,7 @@
gfortran.dg/fmt_t_5.f90, gfortran.dg/namelist_12.f, gfortran.dg/fmt_t_5.f90, gfortran.dg/namelist_12.f,
gfortran.dg/backspace_7.f90, gfortran.dg/write_rewind_2.f, gfortran.dg/backspace_7.f90, gfortran.dg/write_rewind_2.f,
gfortran.dg/ftell_1.f90, gfortran.dg/fseek.f90, gfortran.dg/ftell_1.f90, gfortran.dg/fseek.f90,
gfortran.dg/write_back.f: Gate test on effective_target gfortran.dg/write_back.f: Gate test on effective_target fd_truncate.
fd_truncate.
2008-03-04 Joseph Myers <joseph@codesourcery.com> 2008-03-04 Joseph Myers <joseph@codesourcery.com>
@ -10493,7 +10502,8 @@
2008-01-18 Tobias Burnus <burnus@net-b.de> 2008-01-18 Tobias Burnus <burnus@net-b.de>
* gfortran.dg/large_real_kind_form_io_1.f90: Enlarge string for internal I/O. * gfortran.dg/large_real_kind_form_io_1.f90: Enlarge string for
internal I/O.
2008-01-18 Jonathan Wakely <jwakely.gcc@gmail.com> 2008-01-18 Jonathan Wakely <jwakely.gcc@gmail.com>
@ -11049,8 +11059,8 @@
2008-01-02 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2008-01-02 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
PR middle-end/34562 PR middle-end/34562
* g++.dg/other/first-global.C: Also accept _GLOBAL__I_65535_0_foobar in * g++.dg/other/first-global.C: Also accept _GLOBAL__I_65535_0_foobar
scan-assembler check. in scan-assembler check.
2008-01-03 Jakub Jelinek <jakub@redhat.com> 2008-01-03 Jakub Jelinek <jakub@redhat.com>

58
gcc/testsuite/gfortran.dg/pr37286.f90 Normal file
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@ -0,0 +1,58 @@
! { dg-do compile }
module general_rand
implicit none
private
integer, public, parameter :: GNDP = kind(1.0d0)
real(kind = GNDP), save :: &
gnc = 362436.0 / 16777216.0, &
gncd = 7654321.0 / 16777216.0, &
gncm = 16777213.0 / 16777216.0
integer, save :: &
gni97 = 97, &
gnj97 = 33
real(kind = GNDP), save :: gnu(97)
contains
subroutine gn_fatal(message)
character(len = *), intent(in) :: message
stop 1
end subroutine gn_fatal
function gn_monte_rand(min, max) result(monte)
real(kind = GNDP), intent(in) :: min
real(kind = GNDP), intent(in) :: max
real(kind = GNDP) :: monte
real :: monte_temp
if (min > max) then
call gn_fatal('gn_monte_rand: min > max')
else if (min == max) then
call gn_fatal('gn_monte_rand: min = max: returning min')
monte_temp = min
else
monte_temp = gnu(gni97) - gnu(gnj97)
if (monte_temp < 0.0) then
monte_temp = monte_temp + 1.0
end if
gnu(gni97) = monte_temp
gni97 = gni97 - 1
if (gni97 == 0) then
gni97 = 97
end if
end if
monte = min + monte_temp * (max - min)
end function gn_monte_rand
end module general_rand
! { dg-final { cleanup-modules "general_rand" } }