re PR rtl-optimization/55838 (ICE in extract_insn (unrecognizable insn) with -O -funroll-loops)
PR rtl-optimization/55838 * loop-iv.c (iv_number_of_iterations): Call lowpart_subreg on iv0.step, iv1.step and step. * gcc.dg/pr55838.c: New test. From-SVN: r194837
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4 changed files with 27 additions and 1 deletions
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@ -1,3 +1,9 @@
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2013-01-03 Jakub Jelinek <jakub@redhat.com>
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PR rtl-optimization/55838
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* loop-iv.c (iv_number_of_iterations): Call lowpart_subreg on
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iv0.step, iv1.step and step.
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2013-01-03 Jakub Jelinek <jakub@redhat.com>
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Marc Glisse <marc.glisse@inria.fr>
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/* Rtl-level induction variable analysis.
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Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2010
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Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012, 2013
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Free Software Foundation, Inc.
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This file is part of GCC.
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@ -2406,6 +2406,9 @@ iv_number_of_iterations (struct loop *loop, rtx insn, rtx condition,
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iv1.step = const0_rtx;
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}
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iv0.step = lowpart_subreg (mode, iv0.step, comp_mode);
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iv1.step = lowpart_subreg (mode, iv1.step, comp_mode);
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/* This is either infinite loop or the one that ends immediately, depending
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on initial values. Unswitching should remove this kind of conditions. */
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if (iv0.step == const0_rtx && iv1.step == const0_rtx)
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@ -2516,6 +2519,7 @@ iv_number_of_iterations (struct loop *loop, rtx insn, rtx condition,
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step = simplify_gen_unary (NEG, comp_mode, iv1.step, comp_mode);
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else
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step = iv0.step;
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step = lowpart_subreg (mode, step, comp_mode);
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delta = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base);
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delta = lowpart_subreg (mode, delta, comp_mode);
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delta = simplify_gen_binary (UMOD, mode, delta, step);
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@ -1,5 +1,8 @@
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2013-01-03 Jakub Jelinek <jakub@redhat.com>
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PR rtl-optimization/55838
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* gcc.dg/pr55838.c: New test.
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PR tree-optimization/55832
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* gcc.c-torture/compile/pr55832.c: New test.
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13
gcc/testsuite/gcc.dg/pr55838.c
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13
gcc/testsuite/gcc.dg/pr55838.c
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/* PR rtl-optimization/55838 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -funroll-loops" } */
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int a;
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unsigned char c;
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void
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f (void)
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{
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while (c++ < 2)
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c = a += 129;
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}
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