i386-protos.h (ix86_expand_xorsign): New prototype.
* config/i386/i386-protos.h (ix86_expand_xorsign): New prototype. (ix86_split_xorsign): Ditto. * config/i386/i386.c (ix86_expand_xorsign): New function. (ix86_split_xorsign): Ditto. * config/i386/i386.md (UNSPEC_XORSIGN): New unspec. (xorsign<mode>3): New expander. (xorsign<mode>3_1): New insn_and_split pattern. * config/i386/sse.md (xorsign<mode>3): New expander. testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_xorsign): Add i?86-*-* and x86_64-*-* targets. * gcc.target/i386/xorsign.c: New test. From-SVN: r267779
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
f3ed896c55
commit
33142cf9cf
8 changed files with 170 additions and 1 deletions
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@ -1,3 +1,14 @@
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2019-01-09 Uroš Bizjak <ubizjak@gmail.com>
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* config/i386/i386-protos.h (ix86_expand_xorsign): New prototype.
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(ix86_split_xorsign): Ditto.
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* config/i386/i386.c (ix86_expand_xorsign): New function.
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(ix86_split_xorsign): Ditto.
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* config/i386/i386.md (UNSPEC_XORSIGN): New unspec.
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(xorsign<mode>3): New expander.
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(xorsign<mode>3_1): New insn_and_split pattern.
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* config/i386/sse.md (xorsign<mode>3): New expander.
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2019-01-09 Eric Botcazou <ebotcazou@adacore.com>
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* config/sparc/sparc.md (*tablejump_sp32): Merge into...
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@ -124,6 +124,8 @@ extern void ix86_expand_fp_absneg_operator (enum rtx_code, machine_mode,
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extern void ix86_expand_copysign (rtx []);
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extern void ix86_split_copysign_const (rtx []);
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extern void ix86_split_copysign_var (rtx []);
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extern void ix86_expand_xorsign (rtx []);
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extern void ix86_split_xorsign (rtx []);
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extern bool ix86_unary_operator_ok (enum rtx_code, machine_mode, rtx[]);
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extern bool ix86_match_ccmode (rtx, machine_mode);
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extern void ix86_expand_branch (enum rtx_code, rtx, rtx, rtx);
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@ -21860,6 +21860,63 @@ ix86_split_copysign_var (rtx operands[])
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emit_insn (gen_rtx_SET (dest, x));
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}
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/* Expand an xorsign operation. */
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void
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ix86_expand_xorsign (rtx operands[])
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{
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rtx (*xorsign_insn)(rtx, rtx, rtx, rtx);
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machine_mode mode, vmode;
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rtx dest, op0, op1, mask;
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dest = operands[0];
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op0 = operands[1];
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op1 = operands[2];
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mode = GET_MODE (dest);
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if (mode == SFmode)
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{
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xorsign_insn = gen_xorsignsf3_1;
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vmode = V4SFmode;
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}
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else if (mode == DFmode)
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{
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xorsign_insn = gen_xorsigndf3_1;
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vmode = V2DFmode;
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}
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else
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gcc_unreachable ();
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mask = ix86_build_signbit_mask (vmode, 0, 0);
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emit_insn (xorsign_insn (dest, op0, op1, mask));
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}
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/* Deconstruct an xorsign operation into bit masks. */
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void
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ix86_split_xorsign (rtx operands[])
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{
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machine_mode mode, vmode;
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rtx dest, op0, mask, x;
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dest = operands[0];
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op0 = operands[1];
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mask = operands[3];
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mode = GET_MODE (dest);
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vmode = GET_MODE (mask);
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dest = lowpart_subreg (vmode, dest, mode);
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x = gen_rtx_AND (vmode, dest, mask);
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emit_insn (gen_rtx_SET (dest, x));
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op0 = lowpart_subreg (vmode, op0, mode);
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x = gen_rtx_XOR (vmode, dest, op0);
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emit_insn (gen_rtx_SET (dest, x));
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}
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/* Return TRUE or FALSE depending on whether the first SET in INSN
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has source and destination with matching CC modes, and that the
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CC mode is at least as constrained as REQ_MODE. */
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@ -124,6 +124,7 @@
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;; Generic math support
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UNSPEC_COPYSIGN
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UNSPEC_XORSIGN
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UNSPEC_IEEE_MIN ; not commutative
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UNSPEC_IEEE_MAX ; not commutative
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@ -9784,6 +9785,26 @@
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&& reload_completed"
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[(const_int 0)]
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"ix86_split_copysign_var (operands); DONE;")
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(define_expand "xorsign<mode>3"
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[(match_operand:MODEF 0 "register_operand")
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(match_operand:MODEF 1 "register_operand")
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(match_operand:MODEF 2 "register_operand")]
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"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
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"ix86_expand_xorsign (operands); DONE;")
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(define_insn_and_split "xorsign<mode>3_1"
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[(set (match_operand:MODEF 0 "register_operand" "=Yv")
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(unspec:MODEF
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[(match_operand:MODEF 1 "register_operand" "Yv")
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(match_operand:MODEF 2 "register_operand" "0")
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(match_operand:<ssevecmode> 3 "nonimmediate_operand" "Yvm")]
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UNSPEC_XORSIGN))]
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"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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"ix86_split_xorsign (operands); DONE;")
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;; One complement instructions
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@ -3423,6 +3423,20 @@
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operands[5] = gen_reg_rtx (<MODE>mode);
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})
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(define_expand "xorsign<mode>3"
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[(set (match_dup 4)
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(and:VF (match_dup 3)
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(match_operand:VF 2 "vector_operand")))
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(set (match_operand:VF 0 "register_operand")
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(xor:VF (match_dup 4)
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(match_operand:VF 1 "vector_operand")))]
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"TARGET_SSE"
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{
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operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0);
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operands[4] = gen_reg_rtx (<MODE>mode);
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})
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;; Also define scalar versions. These are used for abs, neg, and
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;; conditional move. Using subregs into vector modes causes register
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;; allocation lossage. These patterns do not allow memory operands
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@ -1,3 +1,9 @@
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2019-01-09 Uroš Bizjak <ubizjak@gmail.com>
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* lib/target-supports.exp
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(check_effective_target_xorsign): Add i?86-*-* and x86_64-*-* targets.
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* gcc.target/i386/xorsign.c: New test.
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2019-01-09 Eric Botcazou <ebotcazou@adacore.com>
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* gcc.target/sparc/tls-ld-int8.c: New test.
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57
gcc/testsuite/gcc.target/i386/xorsign.c
Normal file
57
gcc/testsuite/gcc.target/i386/xorsign.c
Normal file
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@ -0,0 +1,57 @@
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/* { dg-do run { target sse2_runtime } } */
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/* { dg-options "-O2 -msse2 -mfpmath=sse -ftree-vectorize -fdump-tree-vect-details -save-temps" } */
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extern void abort ();
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#define N 16
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float a[N] = {-0.1f, -3.2f, -6.3f, -9.4f,
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-12.5f, -15.6f, -18.7f, -21.8f,
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24.9f, 27.1f, 30.2f, 33.3f,
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36.4f, 39.5f, 42.6f, 45.7f};
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float b[N] = {-1.2f, 3.4f, -5.6f, 7.8f,
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-9.0f, 1.0f, -2.0f, 3.0f,
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-4.0f, -5.0f, 6.0f, 7.0f,
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-8.0f, -9.0f, 10.0f, 11.0f};
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float r[N];
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double ad[N] = {-0.1d, -3.2d, -6.3d, -9.4d,
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-12.5d, -15.6d, -18.7d, -21.8d,
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24.9d, 27.1d, 30.2d, 33.3d,
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36.4d, 39.5d, 42.6d, 45.7d};
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double bd[N] = {-1.2d, 3.4d, -5.6d, 7.8d,
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-9.0d, 1.0d, -2.0d, 3.0d,
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-4.0d, -5.0d, 6.0d, 7.0d,
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-8.0d, -9.0d, 10.0d, 11.0d};
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double rd[N];
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int
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main (void)
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{
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int i;
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for (i = 0; i < N; i++)
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r[i] = a[i] * __builtin_copysignf (1.0f, b[i]);
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/* check results: */
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for (i = 0; i < N; i++)
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if (r[i] != a[i] * __builtin_copysignf (1.0f, b[i]))
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abort ();
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for (i = 0; i < N; i++)
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rd[i] = ad[i] * __builtin_copysign (1.0d, bd[i]);
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/* check results: */
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for (i = 0; i < N; i++)
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if (rd[i] != ad[i] * __builtin_copysign (1.0d, bd[i]))
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abort ();
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return 0;
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}
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/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
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/* { dg-final { scan-assembler "\[ \t\]xor" } } */
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/* { dg-final { scan-assembler "\[ \t\]and" } } */
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/* { dg-final { scan-assembler-not "copysign" } } */
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/* { dg-final { scan-assembler-not "\[ \t\]fxam" } } */
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/* { dg-final { scan-assembler-not "\[ \t\]or" } } */
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/* { dg-final { scan-assembler-not "\[ \t\]mul" } } */
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@ -5730,7 +5730,8 @@ proc check_effective_target_vect_perm3_short { } {
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proc check_effective_target_xorsign { } {
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return [check_cached_effective_target_indexed xorsign {
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expr { [istarget aarch64*-*-*] || [istarget arm*-*-*] }}]
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expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
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|| [istarget aarch64*-*-*] || [istarget arm*-*-*] }}]
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}
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# Return 1 if the target plus current options supports a vector
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