Fix PR target/43154
From-SVN: r157074
This commit is contained in:
Michael Meissner
Michael Meissner
parent
f61ae06585
commit
2fcd8e02d6
7 changed files with 91 additions and 19 deletions
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@ -1,3 +1,22 @@
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2010-02-25 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/43154
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* config/rs6000/vector.md (VEC_64): New iterator for V2DF, V2DI.
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(vec_interleave_high<mode>): Rename from vec_interleave_highv2df
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and support both V2DF and V2DI modes.
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(vec_interleave_low<mode>): Rename from vec_interleave_lowv2df and
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support both V2DF and V2DI modes.
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(general): Delete trailing whitespace from a few patterns.
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* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
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V2DF/V2DI interleave high/low builtins.
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* config/rs6000/rs6000-builtin.def (VSX_BUILTIN_VEC_MERGE*): Add
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new VSX builtins.
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* config/rs6000/rs6000.c (bdesc_2arg): Add support for V2DF/V2DI
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interleave high/low functions.
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2010-02-25 Gerald Pfeifer <gerald@pfeifer.com>
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* doc/extend.texi (Symbol-Renaming Pragmas): Fix spelling of
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@ -955,6 +955,10 @@ RS6000_BUILTIN(VSX_BUILTIN_VEC_SET_V2DF, RS6000_BTC_CONST)
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RS6000_BUILTIN(VSX_BUILTIN_VEC_SET_V2DI, RS6000_BTC_CONST)
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RS6000_BUILTIN(VSX_BUILTIN_VEC_EXT_V2DF, RS6000_BTC_CONST)
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RS6000_BUILTIN(VSX_BUILTIN_VEC_EXT_V2DI, RS6000_BTC_CONST)
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RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEL_V2DF, RS6000_BTC_CONST)
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RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEL_V2DI, RS6000_BTC_CONST)
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RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEH_V2DF, RS6000_BTC_CONST)
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RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEH_V2DI, RS6000_BTC_CONST)
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/* VSX overloaded builtins, add the overloaded functions not present in
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Altivec. */
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@ -1372,6 +1372,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
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RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
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{ ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
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RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
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{ ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
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@ -1416,6 +1420,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
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RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
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{ ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
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RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
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{ ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
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@ -8950,6 +8950,10 @@ static struct builtin_description bdesc_2arg[] =
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{ MASK_VSX, CODE_FOR_vsx_xxmrghw_v4si, "__builtin_vsx_xxmrghw_4si", VSX_BUILTIN_XXMRGHW_4SI },
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{ MASK_VSX, CODE_FOR_vsx_xxmrglw_v4sf, "__builtin_vsx_xxmrglw", VSX_BUILTIN_XXMRGLW_4SF },
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{ MASK_VSX, CODE_FOR_vsx_xxmrglw_v4si, "__builtin_vsx_xxmrglw_4si", VSX_BUILTIN_XXMRGLW_4SI },
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{ MASK_VSX, CODE_FOR_vec_interleave_lowv2df, "__builtin_vsx_mergel_2df", VSX_BUILTIN_VEC_MERGEL_V2DF },
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{ MASK_VSX, CODE_FOR_vec_interleave_lowv2di, "__builtin_vsx_mergel_2di", VSX_BUILTIN_VEC_MERGEL_V2DI },
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{ MASK_VSX, CODE_FOR_vec_interleave_highv2df, "__builtin_vsx_mergeh_2df", VSX_BUILTIN_VEC_MERGEH_V2DF },
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{ MASK_VSX, CODE_FOR_vec_interleave_highv2di, "__builtin_vsx_mergeh_2di", VSX_BUILTIN_VEC_MERGEH_V2DI },
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{ MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
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{ MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
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@ -51,6 +51,9 @@
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;; Vector init/extract modes
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(define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
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;; Vector modes for 64-bit base types
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(define_mode_iterator VEC_64 [V2DI V2DF])
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;; Vector reload iterator
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(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])
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@ -480,7 +483,7 @@
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(eq:SI (reg:CC 74)
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(const_int 0)))]
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"TARGET_ALTIVEC || TARGET_VSX"
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"")
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"")
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(define_expand "cr6_test_for_zero_reverse"
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[(set (match_operand:SI 0 "register_operand" "=r")
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@ -533,7 +536,7 @@
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(not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]
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"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
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"")
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(define_expand "nor<mode>3"
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[(set (match_operand:VEC_L 0 "vlogical_operand" "")
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(not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
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@ -668,24 +671,24 @@
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"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
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"")
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(define_expand "vec_interleave_highv2df"
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[(set (match_operand:V2DF 0 "vfloat_operand" "")
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(vec_concat:V2DF
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(vec_select:DF (match_operand:V2DF 1 "vfloat_operand" "")
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(parallel [(const_int 0)]))
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(vec_select:DF (match_operand:V2DF 2 "vfloat_operand" "")
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(parallel [(const_int 0)]))))]
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"VECTOR_UNIT_VSX_P (V2DFmode)"
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(define_expand "vec_interleave_high<mode>"
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[(set (match_operand:VEC_64 0 "vfloat_operand" "")
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(vec_concat:VEC_64
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(vec_select:<VEC_base> (match_operand:VEC_64 1 "vfloat_operand" "")
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(parallel [(const_int 0)]))
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(vec_select:<VEC_base> (match_operand:VEC_64 2 "vfloat_operand" "")
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(parallel [(const_int 0)]))))]
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"VECTOR_UNIT_VSX_P (<MODE>mode)"
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"")
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(define_expand "vec_interleave_lowv2df"
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[(set (match_operand:V2DF 0 "vfloat_operand" "")
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(vec_concat:V2DF
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(vec_select:DF (match_operand:V2DF 1 "vfloat_operand" "")
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(parallel [(const_int 1)]))
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(vec_select:DF (match_operand:V2DF 2 "vfloat_operand" "")
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(parallel [(const_int 1)]))))]
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"VECTOR_UNIT_VSX_P (V2DFmode)"
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(define_expand "vec_interleave_low<mode>"
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[(set (match_operand:VEC_64 0 "vfloat_operand" "")
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(vec_concat:VEC_64
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(vec_select:<VEC_base> (match_operand:VEC_64 1 "vfloat_operand" "")
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(parallel [(const_int 1)]))
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(vec_select:<VEC_base> (match_operand:VEC_64 2 "vfloat_operand" "")
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(parallel [(const_int 1)]))))]
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"VECTOR_UNIT_VSX_P (<MODE>mode)"
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"")
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@ -889,7 +892,7 @@
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rtx insn;
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HOST_WIDE_INT bitshift_val;
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HOST_WIDE_INT byteshift_val;
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if (! CONSTANT_P (bitshift))
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FAIL;
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bitshift_val = INTVAL (bitshift);
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@ -1,3 +1,8 @@
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2010-02-25 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/43154
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* gcc.target/powerpc/pr43154.c: New file.
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2010-02-25 Jakub Jelinek <jakub@redhat.com>
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PR debug/43166
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29
gcc/testsuite/gcc.target/powerpc/pr43154.c
Normal file
29
gcc/testsuite/gcc.target/powerpc/pr43154.c
Normal file
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@ -0,0 +1,29 @@
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/* { dg-do compile { target { powerpc*-*-* } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_vsx_ok } */
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/* { dg-options "-O2 -mcpu=power7" } */
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/* Make sure that vec_mergel and vec_mergeh are supported for V2DF/V2DI types. */
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/* { dg-final { scan-assembler-times "xxpermdi" 4 } } */
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#include <altivec.h>
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void vec_high_v2df (vector double *a, vector double *b, vector double *c)
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{
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*a = vec_mergeh (*b, *c);
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}
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void vec_low_v2df (vector double *a, vector double *b, vector double *c)
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{
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*a = vec_mergel (*b, *c);
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}
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void vec_high_v2di (vector long long *a, vector long long *b, vector long long *c)
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{
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*a = vec_mergeh (*b, *c);
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}
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void vec_low_v2di (vector long long *a, vector long long *b, vector long long *c)
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{
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*a = vec_mergel (*b, *c);
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}
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