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AArch64 testsuite: Force shrn-combine-*.c to use NEON.

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These tests are testing Advanced SIMD codegen, so if the compiler or the
testsuite is forcing SVE they will fail.

This adds +nosve so that we always generate Advanced SIMD codegen.

gcc/testsuite/ChangeLog:

	PR target/102907
	* gcc.target/aarch64/shrn-combine-1.c: Disable SVE.
	* gcc.target/aarch64/shrn-combine-2.c: Likewise.
	* gcc.target/aarch64/shrn-combine-3.c: Likewise.
	* gcc.target/aarch64/shrn-combine-4.c: Likewise.
	* gcc.target/aarch64/shrn-combine-5.c: Likewise.
	* gcc.target/aarch64/shrn-combine-6.c: Likewise.
	* gcc.target/aarch64/shrn-combine-7.c: Likewise.
This commit is contained in:
Tamar Christina 2021-10-25 15:14:04 +01:00
parent f217e87972
commit 2cbfaba606
7 changed files with 14 additions and 0 deletions
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2
gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c
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@ -1,6 +1,8 @@
/* { dg-do assemble } */
/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
#pragma GCC target "+nosve"
#define TYPE char
void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n)

2
gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c
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@ -1,6 +1,8 @@
/* { dg-do assemble } */
/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
#pragma GCC target "+nosve"
#define TYPE short
void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n)

2
gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c
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@ -1,6 +1,8 @@
/* { dg-do assemble } */
/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
#pragma GCC target "+nosve"
#define TYPE int
void foo (unsigned long long * restrict a, TYPE * restrict d, int n)

2
gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c
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@ -1,6 +1,8 @@
/* { dg-do assemble } */
/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
#pragma GCC target "+nosve"
#define TYPE long long
void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n)

2
gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c
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@ -1,6 +1,8 @@
/* { dg-do assemble } */
/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
#pragma GCC target "+nosve"
#define TYPE1 char
#define TYPE2 short
#define SHIFT 8

2
gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c
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@ -1,6 +1,8 @@
/* { dg-do assemble } */
/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
#pragma GCC target "+nosve"
#define TYPE1 short
#define TYPE2 int
#define SHIFT 16

2
gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c
View file

@ -1,6 +1,8 @@
/* { dg-do assemble } */
/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
#pragma GCC target "+nosve"
#define TYPE1 int
#define TYPE2 long long
#define SHIFT 32