sse.md: Allow V64QI, V32QI, V32HI, V4HI modes.
gcc/ * config/i386/sse.md: Allow V64QI, V32QI, V32HI, V4HI modes. * config/i386/subst.md (define_mode_iterator SUBST_V): Update. (define_mode_iterator SUBST_A): Ditto. (define_subst_attr "mask_operand7"): New. (define_subst_attr "mask_operand10"): New. (define_subst_attr "mask_operand_arg34") : New. (define_subst_attr "mask_expand_op3"): New. (define_subst_attr "mask_mode512bit_condition"): Handle TARGET_AVX512VL. (define_subst_attr "sd_mask_mode512bit_condition"): Ditto. (define_subst_attr "mask_avx512vl_condition"): New. (define_subst_attr "round_mask_operand4"): Ditto. (define_subst_attr "round_mask_scalar_op3"): Delete. (define_subst_attr "round_mask_op4"): New. (define_subst_attr "round_mode512bit_condition"): Allow V8DImode, V16SImode. (define_subst_attr "round_modev8sf_condition"): New. (define_subst_attr "round_modev4sf_condition"): GET_MODE instead of <MODE>mode. (define_subst_attr "round_saeonly_mask_operand4"): New. (define_subst_attr "round_saeonly_mask_op4"): New. (define_subst_attr "round_saeonly_mode512bit_condition"): Allow V8DImode, V16SImode. (define_subst_attr "round_saeonly_modev8sf_condition"): New. (define_subst_attr "mask_expand4_name" "mask_expand4"): New. (define_subst_attr "mask_expand4_args"): New. (define_subst "mask_expand4"): New. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> From-SVN: r213965
This commit is contained in:
Alexander Ivchenko
Kirill Yukhin
parent
e2131cc732
commit
2534573e53
3 changed files with 80 additions and 11 deletions
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@ -1,3 +1,40 @@
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2014-08-14 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/i386/sse.md: Allow V64QI, V32QI, V32HI, V4HI modes.
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* config/i386/subst.md
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(define_mode_iterator SUBST_V): Update.
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(define_mode_iterator SUBST_A): Ditto.
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(define_subst_attr "mask_operand7"): New.
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(define_subst_attr "mask_operand10"): New.
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(define_subst_attr "mask_operand_arg34") : New.
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(define_subst_attr "mask_expand_op3"): New.
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(define_subst_attr "mask_mode512bit_condition"): Handle TARGET_AVX512VL.
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(define_subst_attr "sd_mask_mode512bit_condition"): Ditto.
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(define_subst_attr "mask_avx512vl_condition"): New.
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(define_subst_attr "round_mask_operand4"): Ditto.
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(define_subst_attr "round_mask_scalar_op3"): Delete.
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(define_subst_attr "round_mask_op4"): New.
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(define_subst_attr "round_mode512bit_condition"): Allow V8DImode,
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V16SImode.
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(define_subst_attr "round_modev8sf_condition"): New.
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(define_subst_attr "round_modev4sf_condition"): GET_MODE instead of
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<MODE>mode.
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(define_subst_attr "round_saeonly_mask_operand4"): New.
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(define_subst_attr "round_saeonly_mask_op4"): New.
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(define_subst_attr "round_saeonly_mode512bit_condition"): Allow
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V8DImode, V16SImode.
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(define_subst_attr "round_saeonly_modev8sf_condition"): New.
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(define_subst_attr "mask_expand4_name" "mask_expand4"): New.
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(define_subst_attr "mask_expand4_args"): New.
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(define_subst "mask_expand4"): New.
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2014-08-14 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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@ -471,8 +471,8 @@
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;; Mapping of vector modes to corresponding mask size
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(define_mode_attr avx512fmaskmode
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[(V16QI "HI")
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(V16HI "HI") (V8HI "QI")
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[(V64QI "DI") (V32QI "SI") (V16QI "HI")
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(V32HI "SI") (V16HI "HI") (V8HI "QI") (V4HI "QI")
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(V16SI "HI") (V8SI "QI") (V4SI "QI")
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(V8DI "QI") (V4DI "QI") (V2DI "QI")
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(V16SF "HI") (V8SF "QI") (V4SF "QI")
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@ -20,8 +20,8 @@
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;; Some iterators for extending subst as much as possible
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;; All vectors (Use it for destination)
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(define_mode_iterator SUBST_V
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[V16QI
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V16HI V8HI
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[V64QI V32QI V16QI
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V32HI V16HI V8HI
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V16SI V8SI V4SI
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V8DI V4DI V2DI
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V16SF V8SF V4SF
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@ -31,8 +31,8 @@
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[QI HI SI DI])
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(define_mode_iterator SUBST_A
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[V16QI
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V16HI V8HI
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[V64QI V32QI V16QI
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V32HI V16HI V8HI
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V16SI V8SI V4SI
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V8DI V4DI V2DI
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V16SF V8SF V4SF
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@ -47,16 +47,21 @@
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(define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf
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(define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4")
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(define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6")
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(define_subst_attr "mask_operand7" "mask" "" "%{%8%}%N7")
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(define_subst_attr "mask_operand10" "mask" "" "%{%11%}%N10")
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(define_subst_attr "mask_operand11" "mask" "" "%{%12%}%N11")
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(define_subst_attr "mask_operand18" "mask" "" "%{%19%}%N18")
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(define_subst_attr "mask_operand19" "mask" "" "%{%20%}%N19")
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(define_subst_attr "mask_codefor" "mask" "*" "")
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(define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64)")
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(define_subst_attr "mask_operand_arg34" "mask" "" ", operands[3], operands[4]")
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(define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
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(define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL")
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(define_subst_attr "store_mask_constraint" "mask" "vm" "v")
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(define_subst_attr "store_mask_predicate" "mask" "nonimmediate_operand" "register_operand")
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(define_subst_attr "mask_prefix" "mask" "vex" "evex")
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(define_subst_attr "mask_prefix2" "mask" "maybe_vex" "evex")
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(define_subst_attr "mask_prefix3" "mask" "orig,vex" "evex")
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(define_subst_attr "mask_expand_op3" "mask" "3" "5")
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(define_subst "mask"
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[(set (match_operand:SUBST_V 0)
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@ -85,7 +90,7 @@
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(define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4")
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(define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5")
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(define_subst_attr "sd_mask_codefor" "sd" "*" "")
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(define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64)")
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(define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
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(define_subst "sd"
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[(set (match_operand:SUBST_V 0)
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@ -101,6 +106,7 @@
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(define_subst_attr "round_name" "round" "" "_round")
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(define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4")
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(define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5")
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(define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6")
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(define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6")
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(define_subst_attr "round_op2" "round" "" "%R2")
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(define_subst_attr "round_op3" "round" "" "%R3")
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@ -109,14 +115,18 @@
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(define_subst_attr "round_op6" "round" "" "%R6")
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(define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>")
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(define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>")
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(define_subst_attr "round_mask_scalar_op3" "round" "" "<round_mask_scalar_operand3>")
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(define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>")
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(define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>")
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(define_subst_attr "round_constraint" "round" "vm" "v")
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(define_subst_attr "round_constraint2" "round" "m" "v")
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(define_subst_attr "round_constraint3" "round" "rm" "r")
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(define_subst_attr "round_nimm_predicate" "round" "nonimmediate_operand" "register_operand")
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(define_subst_attr "round_prefix" "round" "vex" "evex")
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(define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode || <MODE>mode == V8DFmode)")
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(define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode
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|| <MODE>mode == V8DFmode
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|| <MODE>mode == V8DImode
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|| <MODE>mode == V16SImode)")
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(define_subst_attr "round_modev8sf_condition" "round" "1" "(<MODE>mode == V8SFmode)")
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(define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode == V4SFmode)")
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(define_subst_attr "round_codefor" "round" "*" "")
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(define_subst_attr "round_opnum" "round" "5" "6")
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@ -133,6 +143,7 @@
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(define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round")
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(define_subst_attr "round_saeonly_mask_operand2" "mask" "%r2" "%r4")
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(define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5")
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(define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6")
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(define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5")
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(define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7")
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(define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2")
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@ -143,12 +154,17 @@
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(define_subst_attr "round_saeonly_prefix" "round_saeonly" "vex" "evex")
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(define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "<round_saeonly_mask_operand2>")
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(define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "<round_saeonly_mask_operand3>")
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(define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>")
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(define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>")
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(define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>")
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(define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v")
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(define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v")
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(define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "nonimmediate_operand" "register_operand")
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(define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode || <MODE>mode == V8DFmode)")
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(define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode
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|| <MODE>mode == V8DFmode
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|| <MODE>mode == V8DImode
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|| <MODE>mode == V16SImode)")
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(define_subst_attr "round_saeonly_modev8sf_condition" "round_saeonly" "1" "(<MODE>mode == V8SFmode)")
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(define_subst "round_saeonly"
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[(set (match_operand:SUBST_A 0)
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@ -196,3 +212,19 @@
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(match_dup 4)
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(match_dup 5)
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(unspec [(match_operand:SI 6 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)])
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(define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask")
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(define_subst_attr "mask_expand4_args" "mask_expand4" "" ", operands[4], operands[5]")
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(define_subst "mask_expand4"
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[(match_operand:SUBST_V 0)
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(match_operand:SUBST_V 1)
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(match_operand:SUBST_V 2)
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(match_operand:SI 3)]
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"TARGET_AVX512VL"
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[(match_dup 0)
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(match_dup 1)
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(match_dup 2)
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(match_dup 3)
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(match_operand:SUBST_V 4 "vector_move_operand")
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(match_operand:<avx512fmaskmode> 5 "register_operand")])
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