configure.host: Enable interpreter for mips64.
* configure.host: Enable interpreter for mips64. Enable hash synchronization for all mips*-*-linux* targets. * sysdep/mips/locks.h (compare_and_swap, compare_and_swap_release) Use __sync_bool_compare_and_swap instead of in-line asm. (release_set, read_barrier, write_barrier): Use __sync_synchronize instead of in-line asm. From-SVN: r128438
This commit is contained in:
David Daney
David Daney
parent
b9baeecdcc
commit
22083efc54
3 changed files with 19 additions and 55 deletions
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@ -1,3 +1,12 @@
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2007-09-12 David Daney <ddaney@avtrex.com>
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* configure.host: Enable interpreter for mips64. Enable hash
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synchronization for all mips*-*-linux* targets.
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* sysdep/mips/locks.h (compare_and_swap, compare_and_swap_release) Use
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__sync_bool_compare_and_swap instead of in-line asm.
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(release_set, read_barrier, write_barrier): Use __sync_synchronize
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instead of in-line asm.
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2007-09-09 Andreas Tobler <a.tobler@schweiz.org>
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2007-09-09 Andreas Tobler <a.tobler@schweiz.org>
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PR libgcj/33326
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PR libgcj/33326
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@ -98,7 +98,7 @@ case "${host}" in
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enable_java_net_default=no
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enable_java_net_default=no
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enable_getenv_properties_default=no
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enable_getenv_properties_default=no
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;;
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;;
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mipsel-*|mips-*)
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mips*-*)
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libgcj_interpreter=yes
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libgcj_interpreter=yes
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;;
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;;
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i686-*|i586-*|i486-*|i386-*)
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i686-*|i586-*|i486-*|i386-*)
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@ -283,11 +283,7 @@ EOF
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sysdeps_dir=mips
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sysdeps_dir=mips
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can_unwind_signal=yes
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can_unwind_signal=yes
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DIVIDESPEC=-fno-use-divide-subroutine
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DIVIDESPEC=-fno-use-divide-subroutine
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case "${host}" in
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enable_hash_synchronization_default=yes
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mipsel*-linux* | mipsisa32el*-linux*)
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enable_hash_synchronization_default=yes
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;;
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esac
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;;
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;;
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powerpc*-*-darwin*)
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powerpc*-*-darwin*)
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enable_hash_synchronization_default=yes
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enable_hash_synchronization_default=yes
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@ -22,29 +22,9 @@ typedef unsigned obj_addr_t __attribute__((__mode__(__pointer__)));
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inline static bool
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inline static bool
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compare_and_swap(volatile obj_addr_t *addr,
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compare_and_swap(volatile obj_addr_t *addr,
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obj_addr_t old,
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obj_addr_t old,
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obj_addr_t new_val)
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obj_addr_t new_val)
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{
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{
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long result;
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return __sync_bool_compare_and_swap(addr, old, new_val);
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__asm__ __volatile__(".set\tpush\n\t"
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".set\tnoreorder\n\t"
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".set\tnomacro\n\t"
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"1:\n\t"
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#if _MIPS_SIM == _ABIO32
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".set\tmips2\n\t"
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#endif
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"ll\t%[result],0(%[addr])\n\t"
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"bne\t%[result],%[old],2f\n\t"
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"move\t%[result],$0\n\t" // delay slot
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"move\t%[result],%[new_val]\n\t"
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"sc\t%[result],0(%[addr])\n\t"
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"beq\t%[result],$0,1b\n\t"
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"nop\n\t" // delay slot
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"2:\n\t"
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".set\tpop"
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: [result] "=&r" (result)
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: [addr] "r" (addr), [new_val] "r" (new_val), [old] "r"(old)
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: "memory");
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return (bool) result;
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}
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}
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// Set *addr to new_val with release semantics, i.e. making sure
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// Set *addr to new_val with release semantics, i.e. making sure
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@ -53,12 +33,7 @@ compare_and_swap(volatile obj_addr_t *addr,
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inline static void
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inline static void
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release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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{
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{
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__asm__ __volatile__(".set\tpush\n\t"
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__sync_synchronize();
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#if _MIPS_SIM == _ABIO32
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".set\tmips2\n\t"
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#endif
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"sync\n\t"
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".set\tpop" : : : "memory");
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*(addr) = new_val;
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*(addr) = new_val;
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}
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}
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@ -67,16 +42,10 @@ release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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// implementation can be the same.
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// implementation can be the same.
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inline static bool
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inline static bool
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compare_and_swap_release(volatile obj_addr_t *addr,
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compare_and_swap_release(volatile obj_addr_t *addr,
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obj_addr_t old,
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obj_addr_t old,
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obj_addr_t new_val)
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obj_addr_t new_val)
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{
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{
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__asm__ __volatile__(".set\tpush\n\t"
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return __sync_bool_compare_and_swap(addr, old, new_val);
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#if _MIPS_SIM == _ABIO32
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".set\tmips2\n\t"
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#endif
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"sync\n\t"
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".set\tpop" : : : "memory");
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return compare_and_swap(addr, old, new_val);
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}
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}
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// Ensure that subsequent instructions do not execute on stale
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// Ensure that subsequent instructions do not execute on stale
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@ -85,12 +54,7 @@ compare_and_swap_release(volatile obj_addr_t *addr,
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inline static void
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inline static void
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read_barrier()
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read_barrier()
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{
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{
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__asm__ __volatile__(".set\tpush\n\t"
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__sync_synchronize();
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#if _MIPS_SIM == _ABIO32
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".set\tmips2\n\t"
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#endif
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"sync\n\t"
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".set\tpop" : : : "memory");
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}
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}
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// Ensure that prior stores to memory are completed with respect to other
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// Ensure that prior stores to memory are completed with respect to other
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@ -98,12 +62,7 @@ read_barrier()
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inline static void
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inline static void
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write_barrier()
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write_barrier()
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{
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{
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__asm__ __volatile__(".set\tpush\n\t"
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__sync_synchronize();
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#if _MIPS_SIM == _ABIO32
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".set\tmips2\n\t"
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#endif
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"sync\n\t"
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".set\tpop" : : : "memory");
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}
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}
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#endif // __SYSDEP_LOCKS_H__
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#endif // __SYSDEP_LOCKS_H__
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