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[AArch64] Fix cost for Q register moves

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2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
  move handling.
  (generic_regmove_cost): Undo raised FP2FP move cost as Q register moves are
  now handled correctly.

From-SVN: r215207
This commit is contained in:
Wilco Dijkstra 2014-09-12 09:42:42 +00:00 • committed by Jiong Wang
parent 3be0766211
commit 20b32e50e2
2 changed files with 9 additions and 5 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2014-09-12 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
move handling.
(generic_regmove_cost): Undo raised FP2FP move cost as Q register moves
are now handled correctly.
2014-09-12 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/aarch64.c (aarch64_register_move_cost): Add cost

7
gcc/config/aarch64/aarch64.c
View file

@ -215,10 +215,7 @@ static const struct cpu_regmove_cost generic_regmove_cost =
NAMED_PARAM (GP2GP, 1),
NAMED_PARAM (GP2FP, 2),
NAMED_PARAM (FP2GP, 2),
/* We currently do not provide direct support for TFmode Q->Q move.
Therefore we need to raise the cost above 2 in order to have
reload handle the situation. */
NAMED_PARAM (FP2FP, 4)
NAMED_PARAM (FP2FP, 2)
};
/* Generic costs for vector insn classes. */
@ -5961,7 +5958,7 @@ aarch64_register_move_cost (enum machine_mode mode,
secondary reload. A general register is used as a scratch to move
the upper DI value and the lower DI value is moved directly,
hence the cost is the sum of three moves. */
if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128)
if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 16)
return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP;
return regmove_cost->FP2FP;