simplify-rtx.c (simplify_binary_operation): Remove fall throughs.
* simplify-rtx.c (simplify_binary_operation) <UDIV, DIV, UMOD, MOD>: Remove fall throughs. Convert 0/x and 0%x into x&0 when x has side-effects. Don't convert x/1.0 into x if we honor signaling NaNs. Convert x/-1.0 into -x if we don't honor signaling NaNs. Convert x/-1 into -x. Optimize x%1 into x&0 if x has side-effects. Optimize x%-1 into 0 (or x&0 if x has side-effects). From-SVN: r80625
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Roger Sayle
Roger Sayle
parent
e0fb1c5c37
commit
1e9b78b094
2 changed files with 109 additions and 43 deletions
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@ -1,3 +1,12 @@
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2004-04-12 Roger Sayle <roger@eyesopen.com>
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* simplify-rtx.c (simplify_binary_operation) <UDIV, DIV, UMOD, MOD>:
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Remove fall throughs. Convert 0/x and 0%x into x&0 when x has
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side-effects. Don't convert x/1.0 into x if we honor signaling NaNs.
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Convert x/-1.0 into -x if we don't honor signaling NaNs. Convert
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x/-1 into -x. Optimize x%1 into x&0 if x has side-effects. Optimize
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x%-1 into 0 (or x&0 if x has side-effects).
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2004-04-11 Aldy Hernandez <aldyh@redhat.com>
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* config/rs6000/rs6000.md: Document why a pattern is not
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@ -1900,70 +1900,127 @@ simplify_binary_operation (enum rtx_code code, enum machine_mode mode,
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break;
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case UDIV:
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/* Convert divide by power of two into shift (divide by 1 handled
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below). */
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if (GET_CODE (trueop1) == CONST_INT
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&& (arg1 = exact_log2 (INTVAL (trueop1))) > 0)
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return simplify_gen_binary (LSHIFTRT, mode, op0, GEN_INT (arg1));
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/* Fall through.... */
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case DIV:
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if (trueop1 == CONST1_RTX (mode))
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/* 0/x is 0 (or x&0 if x has side-effects). */
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if (trueop0 == const0_rtx)
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return side_effects_p (op1)
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? simplify_gen_binary (AND, mode, op1, const0_rtx)
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: const0_rtx;
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/* x/1 is x. */
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if (trueop1 == const1_rtx)
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{
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/* On some platforms DIV uses narrower mode than its
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operands. */
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/* Handle narrowing UDIV. */
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rtx x = gen_lowpart_common (mode, op0);
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if (x)
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return x;
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else if (mode != GET_MODE (op0) && GET_MODE (op0) != VOIDmode)
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if (mode != GET_MODE (op0) && GET_MODE (op0) != VOIDmode)
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return gen_lowpart_SUBREG (mode, op0);
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else
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return op0;
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return op0;
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}
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/* Convert divide by power of two into shift. */
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if (GET_CODE (trueop1) == CONST_INT
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&& (arg1 = exact_log2 (INTVAL (trueop1))) > 0)
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return simplify_gen_binary (LSHIFTRT, mode, op0, GEN_INT (arg1));
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break;
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/* Maybe change 0 / x to 0. This transformation isn't safe for
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modes with NaNs, since 0 / 0 will then be NaN rather than 0.
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Nor is it safe for modes with signed zeros, since dividing
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0 by a negative number gives -0, not 0. */
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if (!HONOR_NANS (mode)
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&& !HONOR_SIGNED_ZEROS (mode)
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&& trueop0 == CONST0_RTX (mode)
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&& ! side_effects_p (op1))
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return op0;
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/* Change division by a constant into multiplication. Only do
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this with -funsafe-math-optimizations. */
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else if (GET_CODE (trueop1) == CONST_DOUBLE
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&& GET_MODE_CLASS (GET_MODE (trueop1)) == MODE_FLOAT
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&& trueop1 != CONST0_RTX (mode)
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&& flag_unsafe_math_optimizations)
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case DIV:
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/* Handle floating point and integers separately. */
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if (GET_MODE_CLASS (mode) == MODE_FLOAT)
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{
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REAL_VALUE_TYPE d;
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REAL_VALUE_FROM_CONST_DOUBLE (d, trueop1);
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/* Maybe change 0.0 / x to 0.0. This transformation isn't
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safe for modes with NaNs, since 0.0 / 0.0 will then be
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NaN rather than 0.0. Nor is it safe for modes with signed
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zeros, since dividing 0 by a negative number gives -0.0 */
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if (trueop0 == CONST0_RTX (mode)
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&& !HONOR_NANS (mode)
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&& !HONOR_SIGNED_ZEROS (mode)
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&& ! side_effects_p (op1))
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return op0;
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/* x/1.0 is x. */
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if (trueop1 == CONST1_RTX (mode)
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&& !HONOR_SNANS (mode))
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return op0;
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if (! REAL_VALUES_EQUAL (d, dconst0))
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if (GET_CODE (trueop1) == CONST_DOUBLE
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&& trueop1 != CONST0_RTX (mode))
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{
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REAL_ARITHMETIC (d, rtx_to_tree_code (DIV), dconst1, d);
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tem = CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
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return simplify_gen_binary (MULT, mode, op0, tem);
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REAL_VALUE_TYPE d;
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REAL_VALUE_FROM_CONST_DOUBLE (d, trueop1);
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/* x/-1.0 is -x. */
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if (REAL_VALUES_EQUAL (d, dconstm1)
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&& !HONOR_SNANS (mode))
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return simplify_gen_unary (NEG, mode, op0, mode);
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/* Change FP division by a constant into multiplication.
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Only do this with -funsafe-math-optimizations. */
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if (flag_unsafe_math_optimizations
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&& !REAL_VALUES_EQUAL (d, dconst0))
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{
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REAL_ARITHMETIC (d, RDIV_EXPR, dconst1, d);
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tem = CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
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return simplify_gen_binary (MULT, mode, op0, tem);
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}
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}
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}
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else
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{
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/* 0/x is 0 (or x&0 if x has side-effects). */
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if (trueop0 == const0_rtx)
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return side_effects_p (op1)
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? simplify_gen_binary (AND, mode, op1, const0_rtx)
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: const0_rtx;
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/* x/1 is x. */
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if (trueop1 == const1_rtx)
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{
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/* Handle narrowing DIV. */
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rtx x = gen_lowpart_common (mode, op0);
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if (x)
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return x;
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if (mode != GET_MODE (op0) && GET_MODE (op0) != VOIDmode)
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return gen_lowpart_SUBREG (mode, op0);
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return op0;
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}
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/* x/-1 is -x. */
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if (trueop1 == constm1_rtx)
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{
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rtx x = gen_lowpart_common (mode, op0);
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if (!x)
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x = (mode != GET_MODE (op0) && GET_MODE (op0) != VOIDmode)
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? gen_lowpart_SUBREG (mode, op0) : op0;
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return simplify_gen_unary (NEG, mode, x, mode);
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}
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}
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break;
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case UMOD:
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/* Handle modulus by power of two (mod with 1 handled below). */
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/* 0%x is 0 (or x&0 if x has side-effects). */
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if (trueop0 == const0_rtx)
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return side_effects_p (op1)
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? simplify_gen_binary (AND, mode, op1, const0_rtx)
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: const0_rtx;
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/* x%1 is 0 (of x&0 if x has side-effects). */
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if (trueop1 == const1_rtx)
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return side_effects_p (op0)
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? simplify_gen_binary (AND, mode, op0, const0_rtx)
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: const0_rtx;
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/* Implement modulus by power of two as AND. */
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if (GET_CODE (trueop1) == CONST_INT
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&& exact_log2 (INTVAL (trueop1)) > 0)
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return simplify_gen_binary (AND, mode, op0,
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GEN_INT (INTVAL (op1) - 1));
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/* Fall through.... */
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break;
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case MOD:
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if ((trueop0 == const0_rtx || trueop1 == const1_rtx)
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&& ! side_effects_p (op0) && ! side_effects_p (op1))
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return const0_rtx;
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/* 0%x is 0 (or x&0 if x has side-effects). */
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if (trueop0 == const0_rtx)
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return side_effects_p (op1)
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? simplify_gen_binary (AND, mode, op1, const0_rtx)
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: const0_rtx;
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/* x%1 and x%-1 is 0 (or x&0 if x has side-effects). */
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if (trueop1 == const1_rtx || trueop1 == constm1_rtx)
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return side_effects_p (op0)
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? simplify_gen_binary (AND, mode, op0, const0_rtx)
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: const0_rtx;
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break;
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case ROTATERT:
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