hppa: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
This change implements __builtin_get_fpsr() and __builtin_set_fpsr(x) to get and set the floating-point status register. They are used to implement pa_atomic_assign_expand_fenv(). 2024-02-02 John David Anglin <danglin@gcc.gnu.org> gcc/ChangeLog: PR target/59778 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR and PA_BUILTIN_SET_FPSR builtins. * (pa_builtins_icode): Declare. * (def_builtin, pa_fpu_init_builtins): New. * (pa_init_builtins): Initialize FPU builtins. * (pa_builtin_decl, pa_expand_builtin_1): New. * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and PA_BUILTIN_SET_FPSR builtins. * (pa_atomic_assign_expand_fenv): New. * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New UNSPECV constants. (get_fpsr, put_fpsr): New expanders. (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New insn patterns.
This commit is contained in:
John David Anglin
parent
922e4599e6
commit
1c3cfb5a95
2 changed files with 298 additions and 1 deletions
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@ -28,6 +28,7 @@ along with GCC; see the file COPYING3. If not see
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#include "target.h"
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#include "rtl.h"
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#include "tree.h"
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#include "gimple.h"
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#include "df.h"
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#include "tm_p.h"
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#include "stringpool.h"
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@ -142,6 +143,7 @@ static void pa_asm_out_destructor (rtx, int);
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#endif
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static void pa_init_builtins (void);
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static rtx pa_expand_builtin (tree, rtx, rtx, machine_mode mode, int);
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static tree pa_builtin_decl (unsigned, bool);
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static rtx hppa_builtin_saveregs (void);
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static void hppa_va_start (tree, rtx);
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static tree hppa_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
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@ -205,6 +207,7 @@ static bool pa_modes_tieable_p (machine_mode, machine_mode);
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static bool pa_can_change_mode_class (machine_mode, machine_mode, reg_class_t);
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static HOST_WIDE_INT pa_starting_frame_offset (void);
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static section* pa_elf_select_rtx_section(machine_mode, rtx, unsigned HOST_WIDE_INT) ATTRIBUTE_UNUSED;
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static void pa_atomic_assign_expand_fenv (tree *, tree *, tree *);
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/* The following extra sections are only used for SOM. */
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static GTY(()) section *som_readonly_data_section;
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@ -314,9 +317,10 @@ static size_t n_deferred_plabels = 0;
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#undef TARGET_INIT_BUILTINS
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#define TARGET_INIT_BUILTINS pa_init_builtins
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#undef TARGET_EXPAND_BUILTIN
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#define TARGET_EXPAND_BUILTIN pa_expand_builtin
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#undef TARGET_BUILTIN_DECL
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#define TARGET_BUILTIN_DECL pa_builtin_decl
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#undef TARGET_REGISTER_MOVE_COST
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#define TARGET_REGISTER_MOVE_COST hppa_register_move_cost
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@ -426,6 +430,9 @@ static size_t n_deferred_plabels = 0;
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#undef TARGET_HAVE_SPECULATION_SAFE_VALUE
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#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
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#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
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#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV pa_atomic_assign_expand_fenv
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struct gcc_target targetm = TARGET_INITIALIZER;
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/* Parse the -mfixed-range= option string. */
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@ -592,6 +599,10 @@ pa_option_override (void)
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enum pa_builtins
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{
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/* FPU builtins. */
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PA_BUILTIN_GET_FPSR,
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PA_BUILTIN_SET_FPSR,
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PA_BUILTIN_COPYSIGNQ,
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PA_BUILTIN_FABSQ,
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PA_BUILTIN_INFQ,
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@ -600,10 +611,48 @@ enum pa_builtins
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};
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static GTY(()) tree pa_builtins[(int) PA_BUILTIN_max];
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static GTY(()) enum insn_code pa_builtins_icode[(int) PA_BUILTIN_max];
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/* Add a PA builtin function with NAME, ICODE, CODE and TYPE. Return the
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function decl or NULL_TREE if the builtin was not added. */
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static tree
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def_builtin (const char *name, enum insn_code icode, enum pa_builtins code,
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tree type)
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{
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tree t
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= add_builtin_function (name, type, code, BUILT_IN_MD, NULL, NULL_TREE);
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if (t)
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{
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pa_builtins[code] = t;
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pa_builtins_icode[code] = icode;
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}
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return t;
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}
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/* Create builtin functions for FPU instructions. */
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static void
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pa_fpu_init_builtins (void)
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{
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tree ftype;
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ftype = build_function_type_list (unsigned_type_node, 0);
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def_builtin ("__builtin_get_fpsr", CODE_FOR_get_fpsr,
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PA_BUILTIN_GET_FPSR, ftype);
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ftype = build_function_type_list (void_type_node, unsigned_type_node, 0);
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def_builtin ("__builtin_set_fpsr", CODE_FOR_set_fpsr,
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PA_BUILTIN_SET_FPSR, ftype);
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}
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static void
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pa_init_builtins (void)
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{
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if (!TARGET_SOFT_FLOAT)
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pa_fpu_init_builtins ();
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#ifdef DONT_HAVE_FPUTC_UNLOCKED
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{
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tree decl = builtin_decl_explicit (BUILT_IN_PUTC_UNLOCKED);
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@ -663,6 +712,92 @@ pa_init_builtins (void)
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}
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}
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/* Implement TARGET_BUILTIN_DECL. */
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static tree
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pa_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
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{
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if (code >= PA_BUILTIN_max)
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return error_mark_node;
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return pa_builtins[code];
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}
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static rtx
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pa_expand_builtin_1 (tree exp, rtx target,
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rtx subtarget ATTRIBUTE_UNUSED,
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machine_mode tmode ATTRIBUTE_UNUSED,
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int ignore ATTRIBUTE_UNUSED)
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{
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tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
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enum pa_builtins code
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= (enum pa_builtins) DECL_MD_FUNCTION_CODE (fndecl);
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enum insn_code icode = pa_builtins_icode[code];
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bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
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call_expr_arg_iterator iter;
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int arg_count = 0;
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rtx pat, op[4];
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tree arg;
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if (nonvoid)
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{
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machine_mode tmode = insn_data[icode].operand[0].mode;
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if (!target
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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op[0] = gen_reg_rtx (tmode);
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else
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op[0] = target;
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}
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else
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op[0] = NULL_RTX;
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FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
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{
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const struct insn_operand_data *insn_op;
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int idx;
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if (arg == error_mark_node)
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return NULL_RTX;
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arg_count++;
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idx = arg_count - !nonvoid;
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insn_op = &insn_data[icode].operand[idx];
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op[arg_count] = expand_normal (arg);
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if (! (*insn_data[icode].operand[idx].predicate) (op[arg_count],
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insn_op->mode))
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op[arg_count] = copy_to_mode_reg (insn_op->mode, op[arg_count]);
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}
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switch (arg_count)
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{
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case 0:
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pat = GEN_FCN (icode) (op[0]);
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break;
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case 1:
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if (nonvoid)
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pat = GEN_FCN (icode) (op[0], op[1]);
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else
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pat = GEN_FCN (icode) (op[1]);
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break;
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case 2:
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pat = GEN_FCN (icode) (op[0], op[1], op[2]);
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break;
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case 3:
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pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
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break;
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default:
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gcc_unreachable ();
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}
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if (!pat)
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return NULL_RTX;
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emit_insn (pat);
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return (nonvoid ? op[0] : const0_rtx);
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}
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static rtx
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pa_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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machine_mode mode ATTRIBUTE_UNUSED,
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@ -673,6 +808,10 @@ pa_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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switch (fcode)
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{
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case PA_BUILTIN_GET_FPSR:
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case PA_BUILTIN_SET_FPSR:
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return pa_expand_builtin_1 (exp, target, subtarget, mode, ignore);
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case PA_BUILTIN_FABSQ:
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case PA_BUILTIN_COPYSIGNQ:
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return expand_call (exp, target, ignore);
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@ -11099,4 +11238,78 @@ pa_function_arg_size (machine_mode mode, const_tree type)
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return (int) CEIL (size, UNITS_PER_WORD);
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}
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/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
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static void
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pa_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
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{
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const unsigned PA_FE_INEXACT = 1;
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const unsigned PA_FE_UNDERFLOW = 2;
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const unsigned PA_FE_OVERFLOW = 4;
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const unsigned PA_FE_DIVBYZERO = 8;
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const unsigned PA_FE_INVALID = 16;
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const unsigned HOST_WIDE_INT PA_FE_ALL_EXCEPT = (PA_FE_INVALID
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| PA_FE_DIVBYZERO
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| PA_FE_OVERFLOW
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| PA_FE_UNDERFLOW
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| PA_FE_INEXACT);
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const unsigned HOST_WIDE_INT PA_FE_EXCEPT_SHIFT = 27;
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tree fenv_var, get_fpsr, set_fpsr, mask, ld_fenv, masked_fenv;
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tree hold_all, new_fenv_var, reload_fenv, restore_fnenv;
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tree get_fpsr_call, set_fpsr_call, update_call, atomic_feraiseexcept;
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if (TARGET_SOFT_FLOAT)
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return;
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/* Generate the equivalent of :
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unsigned int fenv_var;
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fenv_var = __builtin_get_fpsr ();
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unsigned int masked_fenv;
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masked_fenv = fenv_var & mask;
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__builtin_set_fpsr (masked_fenv); */
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fenv_var = create_tmp_var_raw (unsigned_type_node);
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get_fpsr = pa_builtins[PA_BUILTIN_GET_FPSR];
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set_fpsr = pa_builtins[PA_BUILTIN_SET_FPSR];
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mask = build_int_cst (unsigned_type_node,
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~((PA_FE_ALL_EXCEPT << PA_FE_EXCEPT_SHIFT)
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| PA_FE_ALL_EXCEPT));
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get_fpsr_call = build_call_expr (get_fpsr, 0);
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ld_fenv = build4 (TARGET_EXPR, unsigned_type_node,
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fenv_var, get_fpsr_call,
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NULL_TREE, NULL_TREE);
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masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask);
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hold_all = build2 (COMPOUND_EXPR, void_type_node, masked_fenv, ld_fenv);
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set_fpsr_call = build_call_expr (set_fpsr, 1, masked_fenv);
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*hold = build2 (COMPOUND_EXPR, void_type_node, hold_all, set_fpsr_call);
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/* Store the value of masked_fenv to clear the exceptions:
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__builtin_set_fpsr (masked_fenv); */
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*clear = set_fpsr_call;
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/* Generate the equivalent of :
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unsigned int new_fenv_var;
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new_fenv_var = __builtin_get_fpsr ();
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__builtin_set_fpsr (fenv_var);
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__atomic_feraiseexcept (new_fenv_var); */
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new_fenv_var = create_tmp_var_raw (unsigned_type_node);
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reload_fenv = build4 (TARGET_EXPR, unsigned_type_node, new_fenv_var,
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get_fpsr_call, NULL_TREE, NULL_TREE);
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restore_fnenv = build_call_expr (set_fpsr, 1, fenv_var);
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atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
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update_call = build_call_expr (atomic_feraiseexcept, 1,
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fold_convert (integer_type_node,
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new_fenv_var));
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*update = build2 (COMPOUND_EXPR, void_type_node,
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build2 (COMPOUND_EXPR, void_type_node,
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reload_fenv, restore_fnenv), update_call);
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}
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#include "gt-pa.h"
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@ -96,6 +96,8 @@
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UNSPECV_OPC ; outline_prologue_call
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UNSPECV_OEC ; outline_epilogue_call
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UNSPECV_LONGJMP ; builtin_longjmp
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UNSPECV_GET_FPSR ; get floating-point status register
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UNSPECV_SET_FPSR ; set floating-point status register
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])
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;; Maximum pc-relative branch offsets.
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@ -10784,3 +10786,85 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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"ldo 15(%%sp),%1\n\t{dep|depw} %%r0,31,3,%1\n\t{ldcw|ldcw,co} 0(%1),%1"
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[(set_attr "type" "binary")
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(set_attr "length" "12")])
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;; Get floating-point status register.
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(define_expand "get_fpsr"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec_volatile:SI [(const_int 0)] UNSPECV_GET_FPSR))]
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""
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{
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if (TARGET_SOFT_FLOAT)
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FAIL;
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if (TARGET_64BIT)
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emit_insn (gen_get_fpsr_64 (operands[0]));
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else
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emit_insn (gen_get_fpsr_32 (operands[0]));
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DONE;
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})
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;; The floating-point status register is stored to an unused slot in
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;; the frame marker and then loaded to register operand 0. The final
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;; floating-point load restores the T bit in the status register.
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;; The final load might be avoided if a word mode store was used to
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;; store the status register. It is unclear why we need a double-word
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;; store. I suspect PA 1.0 didn't support single-word stores of the
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;; status register.
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(define_insn "get_fpsr_32"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec_volatile:SI [(const_int 0)] UNSPECV_GET_FPSR))]
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"!TARGET_SOFT_FLOAT && !TARGET_64BIT"
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"{fstds|fstd} %%fr0,-16(%%sp)\n\tldw -16(%%sp),%0\n\t{fldds|fldd} -16(%%sp),%%fr0"
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[(set_attr "type" "fpstore_load")
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(set_attr "length" "12")])
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;; The 64-bit pattern is similar to the 32-bit pattern except we need
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;; compute the address of the frame location as long displacements aren't
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;; supported on Linux targets.
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(define_insn "get_fpsr_64"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec_volatile:SI [(const_int 0)] UNSPECV_GET_FPSR))
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(clobber (match_scratch:DI 1 "=&r"))]
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"!TARGET_SOFT_FLOAT && TARGET_64BIT"
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"ldo -40(%%sp),%1\n\tfstd %%fr0,0(%1)\n\tldw 0(%1),%0\n\tfldd 0(%1),%%fr0"
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[(set_attr "type" "fpstore_load")
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(set_attr "length" "16")])
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;; Set floating-point status register.
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(define_expand "set_fpsr"
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[(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPECV_SET_FPSR)]
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""
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{
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if (TARGET_SOFT_FLOAT)
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FAIL;
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if (TARGET_64BIT)
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emit_insn (gen_set_fpsr_64 (operands[0]));
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else
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emit_insn (gen_set_fpsr_32 (operands[0]));
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DONE;
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})
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;; The old T bit is extracted and stored in the new status register.
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(define_insn "set_fpsr_32"
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[(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPECV_SET_FPSR)
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(clobber (match_scratch:SI 1 "=&r"))]
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"!TARGET_SOFT_FLOAT && !TARGET_64BIT"
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"{fstds|fstd} %%fr0,-16(%%sp)\n\tldw -16(%%sp),%1\n\t{extru|extrw,u} %1,25,1,%1\n\t{dep|depw} %1,25,1,%0\n\tstw %0,-16(%%sp)\n\t{fldds|fldd} -16(%%sp),%%fr0"
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[(set_attr "type" "store_fpload")
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(set_attr "length" "24")])
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(define_insn "set_fpsr_64"
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[(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPECV_SET_FPSR)
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(clobber (match_scratch:DI 1 "=&r"))
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(clobber (match_scratch:SI 2 "=&r"))]
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"!TARGET_SOFT_FLOAT && TARGET_64BIT"
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"ldo -40(%%sp),%1\n\tfstd %%fr0,0(%1)\n\tldw 0(%1),%2\n\textrw,u %2,25,1,%2\n\tdepw %2,25,1,%0\n\tstw %0,0(%1)\n\tfldd 0(%1),%%fr0"
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[(set_attr "type" "store_fpload")
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(set_attr "length" "28")])
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