s390.md ("d0", "1"): New mode attributes.
2005-12-14 Adrian Straetling <straetling@de.ibm.com>
* config/s390/s390.md ("d0", "1"): New mode attributes.
("<shift>di3", "<shift>si3"): Merge.
("*<shift>di3_and", "*<shift>si3_and"): Merge.
("ashrdi3", "ashrsi3"): Merge.
("*ashrdi3_cc", "*ashrsi3_cc"): Merge.
("*ashrdi3_cc_and", "*ashrsi3_cc_and"): Merge.
("*ashrdi3_cconly", "*ashrsi3_cconly"): Merge.
("*ashrdi3_cconly_and", "*ashrsi3_cconly_and"): Merge.
("*ashrdi3", "*ashrsi3"): Merge.
("*ashrdi3_and", "*ashrsi3_and"): Merge.
From-SVN: r108516
This commit is contained in:
Adrian Straetling
Ulrich Weigand
parent
56477c21e0
commit
1b48c8cc6a
2 changed files with 92 additions and 171 deletions
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@ -1,3 +1,16 @@
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2005-12-14 Adrian Straetling <straetling@de.ibm.com>
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* config/s390/s390.md ("d0", "1"): New mode attributes.
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("<shift>di3", "<shift>si3"): Merge.
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("*<shift>di3_and", "*<shift>si3_and"): Merge.
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("ashrdi3", "ashrsi3"): Merge.
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("*ashrdi3_cc", "*ashrsi3_cc"): Merge.
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("*ashrdi3_cc_and", "*ashrsi3_cc_and"): Merge.
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("*ashrdi3_cconly", "*ashrsi3_cconly"): Merge.
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("*ashrdi3_cconly_and", "*ashrsi3_cconly_and"): Merge.
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("*ashrdi3", "*ashrsi3"): Merge.
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("*ashrdi3_and", "*ashrsi3_and"): Merge.
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2005-12-14 Adrian Straetling <straetling@de.ibm.com>
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* config/s390/s390.md ("extend<mode>di2", "extend<mode>si2"): Merge.
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@ -299,6 +299,16 @@
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;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
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(define_mode_attr dee [(DF "d") (SF "ee")])
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;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
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;; and "0" in SImode. This allows to combine instructions of which the 31bit
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;; version only operates on one register.
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(define_mode_attr d0 [(DI "d") (SI "0")])
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;; In combination with d0 this allows to combine instructions of which the 31bit
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;; version only operates on one register. The DImode version needs an additional
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;; register for the assembler output.
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(define_mode_attr 1 [(DI "%1,") (SI "")])
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;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
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;; 'ashift' and "srdl" in 'lshiftrt'.
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(define_code_attr lr [(ashift "l") (lshiftrt "r")])
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@ -6208,13 +6218,13 @@
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;;
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;
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; (ashl|lshr)di3 instruction pattern(s).
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; (ashl|lshr)(di|si)3 instruction pattern(s).
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;
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(define_expand "<shift>di3"
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[(set (match_operand:DI 0 "register_operand" "")
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(SHIFT:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
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(define_expand "<shift><mode>3"
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[(set (match_operand:DSI 0 "register_operand" "")
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(SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
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""
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"")
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@ -6227,13 +6237,13 @@
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "*<shift>di3_64"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(SHIFT:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
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"TARGET_64BIT"
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"s<lr>lg\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(define_insn "*<shift><mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
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""
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"s<lr>l<g>\t%0,<1>%Y2"
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[(set_attr "op_type" "RS<E>")
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(set_attr "atype" "reg")])
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(define_insn "*<shift>di3_31_and"
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@ -6246,25 +6256,25 @@
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "*<shift>di3_64_and"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(SHIFT:DI (match_operand:DI 1 "register_operand" "d")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n"))))]
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"TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
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"s<lr>lg\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(define_insn "*<shift><mode>3_and"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n"))))]
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"(INTVAL (operands[3]) & 63) == 63"
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"s<lr>l<g>\t%0,<1>%Y2"
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[(set_attr "op_type" "RS<E>")
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(set_attr "atype" "reg")])
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;
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; ashrdi3 instruction pattern(s).
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; ashr(di|si)3 instruction pattern(s).
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;
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(define_expand "ashrdi3"
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(define_expand "ashr<mode>3"
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[(parallel
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[(set (match_operand:DI 0 "register_operand" "")
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(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "")))
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[(set (match_operand:DSI 0 "register_operand" "")
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(ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "")))
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(clobber (reg:CC CC_REGNUM))])]
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""
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"")
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@ -6302,37 +6312,37 @@
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_cc_64"
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(define_insn "*ashr<mode>3_cc"
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[(set (reg CC_REGNUM)
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
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(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=d")
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(ashiftrt:DI (match_dup 1) (match_dup 2)))]
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"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
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"srag\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(set (match_operand:GPR 0 "register_operand" "=d")
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(ashiftrt:GPR (match_dup 1) (match_dup 2)))]
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"s390_match_ccmode(insn, CCSmode)"
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"sra<g>\t%0,<1>%Y2"
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[(set_attr "op_type" "RS<E>")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_cconly_64"
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(define_insn "*ashr<mode>3_cconly"
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[(set (reg CC_REGNUM)
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
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(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
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(const_int 0)))
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(clobber (match_scratch:DI 0 "=d"))]
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"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
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"srag\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(clobber (match_scratch:GPR 0 "=d"))]
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"s390_match_ccmode(insn, CCSmode)"
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"sra<g>\t%0,<1>%Y2"
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[(set_attr "op_type" "RS<E>")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_64"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
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(define_insn "*ashr<mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_64BIT"
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"srag\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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""
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"sra<g>\t%0,<1>%Y2"
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[(set_attr "op_type" "RS<E>")
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(set_attr "atype" "reg")])
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@ -6376,142 +6386,40 @@
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_cc_64_and"
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(define_insn "*ashr<mode>3_cc_and"
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[(set (reg CC_REGNUM)
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n")))
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(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n")))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=d")
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(ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
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"TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
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&& (INTVAL (operands[3]) & 63) == 63"
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"srag\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_cconly_64_and"
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[(set (reg CC_REGNUM)
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n")))
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(const_int 0)))
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(clobber (match_scratch:DI 0 "=d"))]
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"TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
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&& (INTVAL (operands[3]) & 63) == 63"
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"srag\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_64_and"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n"))))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
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"srag\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(set_attr "atype" "reg")])
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;
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; (ashl|lshr)si3 instruction pattern(s).
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;
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(define_insn "<shift>si3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(SHIFT:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
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""
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"s<lr>l\t%0,%Y2"
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "*<shift>si3_and"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(SHIFT:SI (match_operand:SI 1 "register_operand" "0")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n"))))]
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"(INTVAL (operands[3]) & 63) == 63"
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"s<lr>l\t%0,%Y2"
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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;
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; ashrsi3 instruction pattern(s).
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;
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(define_insn "*ashrsi3_cc"
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[(set (reg CC_REGNUM)
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(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=d")
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(ashiftrt:SI (match_dup 1) (match_dup 2)))]
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"s390_match_ccmode(insn, CCSmode)"
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"sra\t%0,%Y2"
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "*ashrsi3_cconly"
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[(set (reg CC_REGNUM)
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(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=d"))]
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"s390_match_ccmode(insn, CCSmode)"
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"sra\t%0,%Y2"
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "ashrsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
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(clobber (reg:CC CC_REGNUM))]
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""
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"sra\t%0,%Y2"
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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; with implicit ANDs
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(define_insn "*ashrsi3_cc_and"
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[(set (reg CC_REGNUM)
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(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n")))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=d")
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(ashiftrt:SI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
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(set (match_operand:GPR 0 "register_operand" "=d")
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(ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
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"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
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"sra\t%0,%Y2"
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[(set_attr "op_type" "RS")
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"sra<g>\t%0,<1>%Y2"
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[(set_attr "op_type" "RS<E>")
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(set_attr "atype" "reg")])
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(define_insn "*ashrsi3_cconly_and"
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(define_insn "*ashr<mode>3_cconly_and"
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[(set (reg CC_REGNUM)
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(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n")))
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(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n")))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=d"))]
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(clobber (match_scratch:GPR 0 "=d"))]
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"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
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"sra\t%0,%Y2"
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[(set_attr "op_type" "RS")
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"sra<g>\t%0,<1>%Y2"
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[(set_attr "op_type" "RS<E>")
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(set_attr "atype" "reg")])
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(define_insn "*ashrsi3_and"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n"))))
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(define_insn "*ashr<mode>3_and"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
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(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
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(match_operand:SI 3 "const_int_operand" "n"))))
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(clobber (reg:CC CC_REGNUM))]
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"(INTVAL (operands[3]) & 63) == 63"
|
||||
"sra\t%0,%Y2"
|
||||
[(set_attr "op_type" "RS")
|
||||
"sra<g>\t%0,<1>%Y2"
|
||||
[(set_attr "op_type" "RS<E>")
|
||||
(set_attr "atype" "reg")])
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue