loongson.md (<u>div<mode>3, [...]): New patterns.
gcc/ 2008-11-13 Ruan Beihong <ruanbeihong@gmail.com> * config/mips/loongson.md (<u>div<mode>3, <u>mod<mode>3): New patterns. * config/mips/loongson2ef.md (ls2_imult): Handle imul3nc. (ls2_idiv): Likewise idiv3. (ls2_prefetch): New reservation. * config/mips/mips.h (ISA_HAS_PREFETCH): Add TARGET_LOONGSON_2EF. * config/mips/mips.md (type): Add imul3nc and idiv3. (length): Handle idiv3. (any_mod): New code_iterator. (u): Handle MOD and UMOD. (mul<mode>3): Generate mul<mode>3_mul3_ls2ef on Loongson targets. (prefetch): Handle TARGET_LOONGSON_2EF. From-SVN: r141835
This commit is contained in:
Ruan Beihong
Richard Sandiford
parent
a0daa81106
commit
1a0f175dd7
5 changed files with 70 additions and 8 deletions
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@ -1,3 +1,17 @@
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2008-11-13 Ruan Beihong <ruanbeihong@gmail.com>
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* config/mips/loongson.md (<u>div<mode>3, <u>mod<mode>3): New patterns.
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* config/mips/loongson2ef.md (ls2_imult): Handle imul3nc.
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(ls2_idiv): Likewise idiv3.
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(ls2_prefetch): New reservation.
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* config/mips/mips.h (ISA_HAS_PREFETCH): Add TARGET_LOONGSON_2EF.
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* config/mips/mips.md (type): Add imul3nc and idiv3.
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(length): Handle idiv3.
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(any_mod): New code_iterator.
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(u): Handle MOD and UMOD.
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(mul<mode>3): Generate mul<mode>3_mul3_ls2ef on Loongson targets.
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(prefetch): Handle TARGET_LOONGSON_2EF.
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2008-11-13 Jakub Jelinek <jakub@redhat.com>
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PR c++/27017
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@ -473,3 +473,23 @@
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"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
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"punpckl<V_stretch_half_suffix>\t%0,%1,%2"
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[(set_attr "type" "fdiv")])
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;; Integer division and modulus.
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(define_insn "<u>div<mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=&d")
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(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
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(match_operand:GPR 2 "register_operand" "d")))]
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"TARGET_LOONGSON_2EF"
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{ return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands); }
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[(set_attr "type" "idiv3")
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(set_attr "mode" "<MODE>")])
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(define_insn "<u>mod<mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=&d")
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(any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
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(match_operand:GPR 2 "register_operand" "d")))]
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"TARGET_LOONGSON_2EF"
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{ return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands); }
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[(set_attr "type" "idiv3")
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(set_attr "mode" "<MODE>")])
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@ -160,14 +160,14 @@
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;; Reservation for integer multiplication instructions.
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(define_insn_reservation "ls2_imult" 5
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "imul,imul3"))
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(eq_attr "type" "imul,imul3nc"))
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"ls2_alu2,ls2_alu2_core")
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;; Reservation for integer division / remainder instructions.
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;; These instructions use the SRT algorithm and hence take 2-38 cycles.
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(define_insn_reservation "ls2_idiv" 20
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "idiv"))
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(eq_attr "type" "idiv,idiv3"))
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"ls2_alu2,ls2_alu2_core*18")
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;; Reservation for memory load instructions.
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@ -176,6 +176,11 @@
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(eq_attr "type" "load,fpload,mfc,mtc"))
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"ls2_mem")
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(define_insn_reservation "ls2_prefetch" 0
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(and (eq_attr "cpu" "loongson_2e,loongson_2f")
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(eq_attr "type" "prefetch,prefetchx"))
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"ls2_mem")
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;; Reservation for memory store instructions.
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;; With stores we assume they don't alias with dependent loads.
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;; Therefore we set the latency to zero.
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@ -919,6 +919,7 @@ enum mips_code_readable_setting {
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/* ISA has data prefetch instructions. This controls use of 'pref'. */
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#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
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|| TARGET_LOONGSON_2EF \
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|| ISA_MIPS32 \
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|| ISA_MIPS32R2 \
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|| ISA_MIPS64 \
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@ -351,8 +351,10 @@
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;; trap trap if instructions
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;; imul integer multiply 2 operands
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;; imul3 integer multiply 3 operands
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;; imul3nc integer multiply 3 operands without clobbering HI/LO
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;; imadd integer multiply-add
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;; idiv integer divide
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;; idiv integer divide 2 operands
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;; idiv3 integer divide 3 operands
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;; move integer register move ({,D}ADD{,U} with rt = 0)
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;; fmove floating point register move
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;; fadd floating point add/subtract
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@ -376,9 +378,9 @@
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(define_attr "type"
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"unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
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prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
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shift,slt,signext,clz,pop,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,
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fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,
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frsqrt2,multi,nop,ghost"
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shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
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fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
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frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
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(cond [(eq_attr "jal" "!unset") (const_string "call")
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(eq_attr "got" "load") (const_string "load")
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@ -553,7 +555,7 @@
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(ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
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(const_int 8)
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(eq_attr "type" "idiv")
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(eq_attr "type" "idiv,idiv3")
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(symbol_ref "mips_idiv_insns () * 4")
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] (const_int 4)))
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@ -787,6 +789,10 @@
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;; from the same template.
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(define_code_iterator any_div [div udiv])
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;; This code iterator allows unsigned and signed modulus to be generated
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;; from the same template.
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(define_code_iterator any_mod [mod umod])
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;; This code iterator allows all native floating-point comparisons to be
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;; generated from the same template.
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(define_code_iterator fcond [unordered uneq unlt unle eq lt le])
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@ -809,6 +815,7 @@
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;; "u" when doing an unsigned operation.
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(define_code_attr u [(sign_extend "") (zero_extend "u")
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(div "") (udiv "u")
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(mod "") (umod "u")
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(gt "") (gtu "u")
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(ge "") (geu "u")
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(lt "") (ltu "u")
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@ -1357,7 +1364,10 @@
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(match_operand:GPR 2 "register_operand")))]
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""
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{
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if (ISA_HAS_<D>MUL3)
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if (TARGET_LOONGSON_2EF)
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emit_insn (gen_mul<mode>3_mul3_ls2ef (operands[0], operands[1],
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operands[2]));
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else if (ISA_HAS_<D>MUL3)
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emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
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else if (TARGET_FIX_R4000)
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emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
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@ -1367,6 +1377,15 @@
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DONE;
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})
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(define_insn "mul<mode>3_mul3_ls2ef"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(mult:GPR (match_operand:GPR 1 "register_operand" "d")
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(match_operand:GPR 2 "register_operand" "d")))]
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"TARGET_LOONGSON_2EF"
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"<d>multu.g\t%0,%1,%2"
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[(set_attr "type" "imul3nc")
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(set_attr "mode" "<MODE>")])
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(define_insn "mul<mode>3_mul3"
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[(set (match_operand:GPR 0 "register_operand" "=d,l")
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(mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
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@ -6128,6 +6147,9 @@
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(match_operand 2 "const_int_operand" "n"))]
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"ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
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{
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if (TARGET_LOONGSON_2EF)
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/* Loongson 2[ef] use load to $0 to perform prefetching. */
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return "ld\t$0,%a0";
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operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
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return "pref\t%1,%a0";
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}
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