RISC-V: bitmanip: add splitter to use bexti for "(a & (1 << BIT_NO)) ? 0 : -1"

Consider creating a polarity-reversed mask from a set-bit (i.e., if
the bit is set, produce all-ones; otherwise: all-zeros).  Using Zbb,
this can be expressed as bexti, followed by an addi of minus-one.  To
enable the combiner to discover this opportunity, we need to split the
canonical expression for "(a & (1 << BIT_NO)) ? 0 : -1" into a form
combinable into bexti.

Consider the function:
    long f(long a)
    {
      return (a & (1 << BIT_NO)) ? 0 : -1;
    }
This produces the following sequence prior to this change:
	andi	a0,a0,16
	seqz	a0,a0
	neg	a0,a0
	ret
Following this change, it results in:
	bexti	a0,a0,4
	addi	a0,a0,-1
	ret

gcc/ChangeLog:

	* config/riscv/bitmanip.md: Add a splitter to generate
	  polarity-reversed masks from a set bit using bexti + addi.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbs-bexti.c: New test.
This commit is contained in:
Philipp Tomsich 2021-11-09 18:54:54 +01:00
parent 705bae2351
commit 1957bedf29
2 changed files with 14 additions and 1 deletions

View file

@ -429,3 +429,16 @@
(const_int 1)
(match_dup 2)))
(set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))])
;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 })
;; using a bext(i) followed by an addi instruction.
;; This splits the canonical representation of "(a & (1 << BIT_NO)) ? 0 : -1".
(define_split
[(set (match_operand:GPR 0 "register_operand")
(neg:GPR (eq:GPR (zero_extract:GPR (match_operand:GPR 1 "register_operand")
(const_int 1)
(match_operand 2))
(const_int 0))))]
"TARGET_ZBS"
[(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2)))
(set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))])

View file

@ -26,6 +26,6 @@ long bexti64_4(long a, char bitno)
}
/* { dg-final { scan-assembler-times "bexti\t" 4 } } */
/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */
/* { dg-final { scan-assembler-times "xori\t" 1 } } */
/* { dg-final { scan-assembler-times "addi\t" 1 } } */
/* { dg-final { scan-assembler-times "neg\t" 1 } } */