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LoongArch: Don't emit dbar 0x700 if -mld-seq-sa

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This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that
two loads on the same address won't be reordered with each other".  Thus
we can omit the "load-load" barrier dbar 0x700.

This is only a micro-optimization because dbar 0x700 is already treated
as nop if the hardware supports LD_SEQ_SA.

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_print_operand): Don't
	print dbar 0x700 if TARGET_LD_SEQ_SA.
	* config/loongarch/sync.md (atomic_load<mode>): Likewise.
This commit is contained in:
Xi Ruoyao 2023-11-16 09:30:14 +08:00
parent 5d3d605553
commit 181ed726b2
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GPG key ID: ACAAD20E19E710E3
2 changed files with 6 additions and 5 deletions
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2
gcc/config/loongarch/loongarch.cc
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@ -6061,7 +6061,7 @@ loongarch_print_operand (FILE *file, rtx op, int letter)
if (loongarch_cas_failure_memorder_needs_acquire (
memmodel_from_int (INTVAL (op))))
fputs ("dbar\t0b10100", file);
else
else if (!TARGET_LD_SEQ_SA)
fputs ("dbar\t0x700", file);
break;

9
gcc/config/loongarch/sync.md
View file

@ -119,13 +119,14 @@
case MEMMODEL_SEQ_CST:
return "dbar\t0x11\\n\\t"
"ld.<size>\t%0,%1\\n\\t"
"dbar\t0x14\\n\\t";
"dbar\t0x14";
case MEMMODEL_ACQUIRE:
return "ld.<size>\t%0,%1\\n\\t"
"dbar\t0x14\\n\\t";
"dbar\t0x14";
case MEMMODEL_RELAXED:
return "ld.<size>\t%0,%1\\n\\t"
"dbar\t0x700\\n\\t";
return TARGET_LD_SEQ_SA ? "ld.<size>\t%0,%1\\n\\t"
: "ld.<size>\t%0,%1\\n\\t"
"dbar\t0x700";
default:
/* The valid memory order variants are __ATOMIC_RELAXED, __ATOMIC_SEQ_CST,