rs6000.c (rs6000_option_override_internal): Add comments to explain why certain error messages make mention of undocumented...
gcc/ChangeLog: 2016-07-22 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/rs6000.c (rs6000_option_override_internal): Add comments to explain why certain error messages make mention of undocumented options. (rs6000_invalid_builtin): Change error messages to replace mention of undocumented options with mention of the -mcpu=power9 option that enables those undocumented options. * config/rs6000/rs6000.h (MASK_FLOAT128): New macro. (RS6000_BTM_FLOAT128): Use the new MASK_FLOAT128 macro in the definition of this macro to correct an existing error. * config/rs6000/rs6000.opt: Add the Undocumented qualifier to the mpower9-fusion, mpower9-vector, mpower9-dform, and mmodulo entries. * doc/extend.texi (PowerPC AltiVec Built-in Functions): Modify descriptions of built-in functions so that they depend on -mcpu=power9 instead of on the corresponding undocumented flags. * doc/invoke.texi (Option Summary): Remove all mention of newly undocumented flags. (IBM RS/6000 and PowerPC Options): Likewise. * doc/md.texi (Constraints for Particuliar Machines): Remove all mention of newly undocumented flags. From-SVN: r238648
This commit is contained in:
Kelvin Nilsen
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1610d41097
7 changed files with 62 additions and 62 deletions
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@ -1,3 +1,25 @@
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2016-07-22 Kelvin Nilsen <kelvin@gcc.gnu.org>
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* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
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comments to explain why certain error messages make mention of
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undocumented options.
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(rs6000_invalid_builtin): Change error messages to replace mention
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of undocumented options with mention of the -mcpu=power9 option
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that enables those undocumented options.
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* config/rs6000/rs6000.h (MASK_FLOAT128): New macro.
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(RS6000_BTM_FLOAT128): Use the new MASK_FLOAT128 macro in the
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definition of this macro to correct an existing error.
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* config/rs6000/rs6000.opt: Add the Undocumented qualifier to the
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mpower9-fusion, mpower9-vector, mpower9-dform, and mmodulo entries.
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* doc/extend.texi (PowerPC AltiVec Built-in Functions): Modify
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descriptions of built-in functions so that they depend on
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-mcpu=power9 instead of on the corresponding undocumented flags.
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* doc/invoke.texi (Option Summary): Remove all mention of newly
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undocumented flags.
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(IBM RS/6000 and PowerPC Options): Likewise.
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* doc/md.texi (Constraints for Particuliar Machines): Remove all
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mention of newly undocumented flags.
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2016-07-22 Evgeny Stupachenko <evstupac@gmail.com>
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* ipa-cp.c (determine_versionability): Do not create constprop clones,
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@ -4212,6 +4212,10 @@ rs6000_option_override_internal (bool global_init_p)
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{
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if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
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{
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/* We prefer to not mention undocumented options in
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error messages. However, if users have managed to select
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power9-fusion without selecting power8-fusion, they
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already know about undocumented flags. */
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error ("-mpower9-fusion requires -mpower8-fusion");
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rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
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}
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@ -4259,6 +4263,10 @@ rs6000_option_override_internal (bool global_init_p)
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/* ISA 3.0 vector instructions include ISA 2.07. */
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if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
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{
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/* We prefer to not mention undocumented options in
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error messages. However, if users have managed to select
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power9-vector without selecting power8-vector, they
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already know about undocumented flags. */
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if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
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error ("-mpower9-vector requires -mpower8-vector");
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rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
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@ -4286,6 +4294,10 @@ rs6000_option_override_internal (bool global_init_p)
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/* ISA 3.0 D-form instructions require p9-vector and upper-regs. */
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if ((TARGET_P9_DFORM_SCALAR || TARGET_P9_DFORM_VECTOR) && !TARGET_P9_VECTOR)
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{
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/* We prefer to not mention undocumented options in
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error messages. However, if users have managed to select
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power9-dform without selecting power9-vector, they
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already know about undocumented flags. */
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if (rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR)
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error ("-mpower9-dform requires -mpower9-vector");
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rs6000_isa_flags &= ~(OPTION_MASK_P9_DFORM_SCALAR
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@ -4294,6 +4306,10 @@ rs6000_option_override_internal (bool global_init_p)
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if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_DF)
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{
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/* We prefer to not mention undocumented options in
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error messages. However, if users have managed to select
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power9-dform without selecting upper-regs-df, they
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already know about undocumented flags. */
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if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
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error ("-mpower9-dform requires -mupper-regs-df");
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rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
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@ -15507,13 +15523,13 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode)
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else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
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error ("Builtin function %s requires the -mpower8-vector option", name);
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else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
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error ("Builtin function %s requires the -mpower9-vector option", name);
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error ("Builtin function %s requires the -mcpu=power9 option", name);
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else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
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== (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
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error ("Builtin function %s requires the -mpower9-misc and"
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error ("Builtin function %s requires the -mcpu=power9 and"
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" -m64 options", name);
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else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
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error ("Builtin function %s requires the -mpower9-misc option", name);
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error ("Builtin function %s requires the -mcpu=power9 option", name);
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else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
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== (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
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error ("Builtin function %s requires the -mhard-float and"
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@ -638,6 +638,7 @@ extern int rs6000_vector_align[];
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#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
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#define MASK_DLMZB OPTION_MASK_DLMZB
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#define MASK_EABI OPTION_MASK_EABI
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#define MASK_FLOAT128 OPTION_MASK_FLOAT128
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#define MASK_FPRND OPTION_MASK_FPRND
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#define MASK_P8_FUSION OPTION_MASK_P8_FUSION
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#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
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@ -2716,7 +2717,7 @@ extern int frame_pointer_needed;
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#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
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#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
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#define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
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#define RS6000_BTM_FLOAT128 MASK_P9_VECTOR /* IEEE 128-bit float. */
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#define RS6000_BTM_FLOAT128 MASK_FLOAT128 /* IEEE 128-bit float. */
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#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
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| RS6000_BTM_VSX \
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@ -606,7 +606,7 @@ Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
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Analyze and remove doubleword swaps from VSX computations.
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mpower9-fusion
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Target Report Mask(P9_FUSION) Var(rs6000_isa_flags)
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Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags)
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Fuse certain operations together for better performance on power9.
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mpower9-misc
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@ -614,7 +614,7 @@ Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
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Use/do not use certain scalar instructions added in ISA 3.0.
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mpower9-vector
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Target Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
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Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
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Use/do not use vector instructions added in ISA 3.0.
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mpower9-dform-scalar
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@ -626,7 +626,7 @@ Target Undocumented Mask(P9_DFORM_VECTOR) Var(rs6000_isa_flags)
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Use/do not use vector register+offset memory instructions added in ISA 3.0.
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mpower9-dform
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Target Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
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Target Undocumented Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
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Use/do not use register+offset memory instructions added in ISA 3.0.
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mpower9-minmax
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@ -638,7 +638,7 @@ Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
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Fuse medium/large code model toc references with the memory instruction.
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mmodulo
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Target Report Mask(MODULO) Var(rs6000_isa_flags)
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Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
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Generate the integer modulo instructions.
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mfloat128
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@ -17523,8 +17523,8 @@ int __builtin_bcdsub_gt (vector __int128_t, vector__int128_t);
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int __builtin_bcdsub_ov (vector __int128_t, vector__int128_t);
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@end smallexample
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If the ISA 3.0 additions to the vector/scalar (power9-vector)
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instruction set are available:
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If the ISA 3.0 instruction set additions (@option{-mcpu=power9})
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are available:
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@smallexample
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vector long long vec_vctz (vector long long);
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@ -17560,9 +17560,8 @@ vector long long vec_vprtybd (vector long long);
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vector unsigned long long vec_vprtybd (vector unsigned long long);
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@end smallexample
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If the ISA 3.0 additions to the vector/scalar (power9-vector)
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instruction set are available for 64-bit targets:
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On 64-bit targets, if the ISA 3.0 additions (@option{-mcpu=power9})
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are available:
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@smallexample
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vector long vec_vprtyb (vector long);
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@ -17578,8 +17577,7 @@ vector __uint128_t vec_vprtybd (vector __uint128_t);
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@end smallexample
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The following built-in vector functions are available for the PowerPC family
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of processors, starting with ISA 3.0 or later (@option{-mcpu=power9})
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or with @option{-mpower9-vector}:
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of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}):
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@smallexample
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__vector unsigned char
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vec_slv (__vector unsigned char src, __vector unsigned char shift_distance);
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@ -17612,8 +17610,7 @@ result returned from the @code{vec_srv} function is a
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with this resulting value coerced to the @code{unsigned char} type.
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The following built-in functions are available for the PowerPC family
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of processors, starting with ISA 3.0 or later (@option{-mcpu=power9})
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or with @option{-mpower9-vector}:
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of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}):
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@smallexample
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__vector unsigned char
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vec_absd (__vector unsigned char arg1, __vector unsigned char arg2);
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@ -17696,9 +17693,9 @@ The second argument to the @var{__builtin_crypto_vshasigmad} and
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integer that is 0 or 1. The third argument to these builtin functions
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must be a constant integer in the range of 0 to 15.
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If the ISA 3.0 additions to the vector/scalar (power9-vector)
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instruction set are available, the following additional functions are
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available for both 32-bit and 64-bit targets.
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If the ISA 3.0 instruction set additions
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are enabled (@option{-mcpu=power9}), the following additional
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functions are available for both 32-bit and 64-bit targets.
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vector short vec_xl (int, vector short *);
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vector short vec_xl (int, short *);
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@ -1011,10 +1011,9 @@ See RS/6000 and PowerPC Options.
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-mcompat-align-parm -mno-compat-align-parm @gol
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-mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf @gol
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-mupper-regs-di -mno-upper-regs-di @gol
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-mupper-regs -mno-upper-regs -mmodulo -mno-modulo @gol
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-mupper-regs -mno-upper-regs @gol
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-mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware @gol
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-mpower9-fusion -mno-mpower9-fusion -mpower9-vector -mno-power9-vector @gol
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-mpower9-dform -mno-power9-dform -mlra -mno-lra}
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-mlra -mno-lra}
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@emph{RX Options}
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@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
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@ -20116,8 +20115,7 @@ following options:
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-mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol
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-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol
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-mcrypto -mdirect-move -mhtm -mpower8-fusion -mpower8-vector @gol
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-mquad-memory -mquad-memory-atomic -mmodulo -mfloat128 -mfloat128-hardware @gol
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-mpower9-fusion -mpower9-vector -mpower9-dform}
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-mquad-memory -mquad-memory-atomic -mfloat128 -mfloat128-hardware}
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The particular options set for any particular CPU varies between
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compiler versions, depending on what setting seems to produce optimal
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@ -20361,7 +20359,7 @@ instructions that target all 64 registers in the vector/scalar
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floating point register set that were added in version 2.07 of the
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PowerPC ISA. @option{-mupper-regs-sf} is turned on by default if you
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use either of the @option{-mcpu=power8}, @option{-mpower8-vector}, or
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@option{-mpower9} options.
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@option{-mcpu=power9} options.
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@item -mupper-regs
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@itemx -mno-upper-regs
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@ -20406,40 +20404,6 @@ If you select ISA 3.0 instructions with @option{-mcpu=power9}, but do
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not use either @option{-mfloat128} or @option{-mfloat128-hardware},
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the IEEE 128-bit floating point support will not be enabled.
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@item -mmodulo
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@itemx -mno-modulo
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@opindex mmodulo
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@opindex mno-module
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Generate code that uses (does not use) the ISA 3.0 integer modulo
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instructions. The @option{-mmodulo} option is enabled by default
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with the @option{-mcpu=power9} option.
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@item -mpower9-fusion
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@itemx -mno-power9-fusion
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@opindex mpower9-fusion
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@opindex mno-power9-fusion
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Generate code that keeps (does not keeps) some operations adjacent so
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that the instructions can be fused together on power9 and later
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processors.
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@item -mpower9-vector
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@itemx -mno-power9-vector
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@opindex mpower9-vector
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@opindex mno-power9-vector
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Generate code that uses (does not use) the vector and scalar
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instructions that were added in version 3.0 of the PowerPC ISA. Also
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enable the use of built-in functions that allow more direct access to
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the vector instructions.
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@item -mpower9-dform
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@itemx -mno-power9-dform
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@opindex mpower9-dform
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@opindex mno-power9-dform
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Enable (disable) scalar d-form (register + offset) memory instructions
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to load/store traditional Altivec registers. If the @var{LRA} register
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allocator is enabled, also enable (disable) vector d-form memory
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instructions.
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@item -mfloat-gprs=@var{yes/single/double/no}
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@itemx -mfloat-gprs
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@opindex mfloat-gprs
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@ -3038,13 +3038,13 @@ asm ("xsaddqp %x0,%x1,%x2" : "=v" (v1) : "v" (v2), "v" (v3));
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is incorrect.
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@item wb
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Altivec register if @option{-mpower9-dform} is used or NO_REGS.
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Altivec register if @option{-mcpu=power9} is used or NO_REGS.
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@item wd
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VSX vector register to hold vector double data or NO_REGS.
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@item we
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VSX register if the @option{-mpower9-vector} and @option{-m64} options
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VSX register if the @option{-mcpu=power9} and @option{-m64} options
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were used or NO_REGS.
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@item wf
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