RISC-V: Minimal support of bitmanip extension

2021-10-25  Kito Cheng  <kito.cheng@sifive.com>

gcc/ChangeLog:

	* common/config/riscv/riscv-common.c (riscv_ext_version_table):
	Add zba, zbb, zbc and zbs.
	(riscv_ext_flag_table): Ditto.
	* config/riscv/riscv-opts.h (MASK_ZBA): New.
	(MASK_ZBB): Ditto.
	(MASK_ZBC): Ditto.
	(MASK_ZBS): Ditto.
	(TARGET_ZBA): Ditto.
	(TARGET_ZBB): Ditto.
	(TARGET_ZBC): Ditto.
	(TARGET_ZBS): Ditto.
	* config/riscv/riscv.opt (riscv_zb_subext): New.
This commit is contained in:
Kito Cheng 2021-08-23 11:19:52 +08:00
parent 1a07bc9cda
commit 149e217033
3 changed files with 23 additions and 0 deletions

View file

@ -101,6 +101,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
/* Terminate the list. */
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
@ -906,6 +911,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
{"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
{"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA},
{"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB},
{"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC},
{"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS},
{NULL, NULL, 0}
};

View file

@ -73,4 +73,14 @@ enum stack_protector_guard {
#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
#define MASK_ZBA (1 << 0)
#define MASK_ZBB (1 << 1)
#define MASK_ZBC (1 << 2)
#define MASK_ZBS (1 << 3)
#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
#endif /* ! GCC_RISCV_OPTS_H */

View file

@ -195,6 +195,9 @@ long riscv_stack_protector_guard_offset = 0
TargetVariable
int riscv_zi_subext
TargetVariable
int riscv_zb_subext
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):