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RISC-V: Add early clobber to the dest of vwsll

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We missed the existing early clobber for the dest operand of vwsll
pattern when resolve the conflict of revert register overlap.  Thus
add it back to the pattern.  Unfortunately, we have no test to cover
this part and will improve this after GCC-15 open.

The below tests are passed for this patch:
* The rv64gcv fully regression test with isl build.

gcc/ChangeLog:

	* config/riscv/vector-crypto.md: Add early clobber to the
	dest operand of vwsll.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li 2024-04-25 08:55:08 +08:00
parent c058105bc4
commit 10ad46bc19
1 changed files with 1 additions and 1 deletions
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2
gcc/config/riscv/vector-crypto.md
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@ -303,7 +303,7 @@
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
(define_insn "@pred_vwsll<mode>_scalar"
[(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
[(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr")
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")